The ILKNF IP provides status flag ports to enable ease of integration into user monitoring and interrupt logic. The following table has a list of the status flags. All status ports are outputs.
Furthermore, many of the status signals can be connected to the increment input of counters in the user logic. This allows you to track statistics for those events.
| Port Name | Clock Domain | I/O | Description |
|---|---|---|---|
| c0_stat_tx_underflow_err | c0_axi_clk | O | TX underflow. This signal indicates whether the core clock for the ILKNF subsystem is too slow to properly fill the link with data. In normal operation, this signal is always sampled as 0. If this signal is sampled as 1, the clocks are not set to proper frequencies and must be fixed. When c0_stat_tx_underflow_err has been asserted, the ILKNF subsystem TX core must be reset. |
| c0_stat_tx_burst_err | c0_axi_clk | O | TX burst error. This signal indicates that the TX AXI-S rules have been violated. Consequently, a burst (that is, a sequence of data words between two control words) that violates BurstShort rules can be sent to the TX Interlaken. When c0_stat_tx_burst_err has been asserted, the ILKNF subsystem TX core must be reset. |
| c0_stat_tx_enain_err | c0_axi_clk | O | Reserved |
| c0_stat_tx_fifo1_oflow_err | c0_axi_clk | O | TX FIFO1 overflow error. When asserted, the TX path of the ILKNF subsystem must be reset. |
| c0_stat_tx_fifo1_uflow_err | c0_axi_clk | O | TX FIFO1 underflow error. When asserted, the TX path of the ILKNF subsystem must be reset. |
| c0_stat_tx_fifo2_oflow_err | c0_axi_clk | O | TX FIFO2 overflow error. When asserted, the TX path of the ILKNF subsystem must be reset. |
| c0_stat_tx_fifo2_uflow_err | c0_axi_clk | O | TX FIFO2 underflow error. When asserted, the TX path of the ILKNF subsystem must be reset. |
| c0_stat_tx_overflow_err | c0_axi_clk | O | TX overflow. This output should never be asserted and indicates a critical failure. In this case, the TX path of the ILKNF subsystem must be reset. |
| Port Name | Clock Domain | I/O | Description |
|---|---|---|---|
| stat_rx_word_sync[23:0] | c0_axi_clk | O | 64B/67B word boundary locked. These signals indicate whether a lane is 64B/67B word boundary locked. A 64B/67B word boundary lock occurs if a lane detects 64 consecutive valid framing patterns on bits[65:64] as per the Interlaken Protocol Definition, Revision 1.2, section 5.4.2. These signals are independent of both the meta frame synchronization word and scrambler state control word. A value of 1 indicates the corresponding lane has achieved 64B/67B word boundary lock. All bits are synced with c0_axi_clk. |
| stat_rx_synced[23:0] | c0_axi_clk | O | Word boundary synchronized. These signals indicate whether a lane is word boundary synchronized. A value of 1 indicates the corresponding lane has achieved word boundary synchronization as follows: a) 64B/67B word boundary locked, b) Correctly receiving the meta frame synchronization word, and c) Correctly receiving the scrambler state control word as described in sections 5.4.2, 5.4.3, and 5.4.4 of the Interlaken Protocol Definition, Revision 1.2. All bits are synced with c0_axi_clk. |
| stat_rx_synced_err[23:0] | c0_axi_clk | O | Word boundary synchronization error. These signals indicate whether an error occurred during word boundary synchronization in the respective lane. A value of 1 indicates the corresponding lane had a word boundary synchronization error. These signals also indicate a mismatch in the descrambler word. All bits are synced with c0_axi_clk. |
| c0_stat_rx_aligned | c0_axi_clk | O | All lanes aligned/de-skewed. A value of 1 indicates all lanes are aligned and de-skewed. When this signal is a 1, the RX path is aligned and can receive packet data. |
| c0_stat_rx_misaligned | c0_axi_clk | O | Alignment error. This signal indicates that the lane aligner in the ILKNF subsystem did not receive the expected meta frame synchronization word across all (active) lanes. This signal can be used to collect the statistic RX_Alignment_Error as described in Table 5-9 of the Interlaken Protocol Definition, Revision 1.2. This signal is not asserted until the meta frame synchronization word has been received at least once across all lanes. A value of 1 indicates the error occurred. |
| c0_stat_rx_aligned_err | c0_axi_clk | O | Loss of lane alignment/de-skew. This signal indicates an error occurred during lane alignment or lane alignment was lost. A value of 1 indicates an error occurred. |
| stat_rx_framing_err[23:0] | c0_axi_clk | O | Framing error. These signals indicate that an illegal framing pattern was detected in the respective lane. A value of 1 indicates an error occurred. All bits are synced with c0_axi_clk. |
| stat_rx_bad_type_err[23:0] | c0_axi_clk | O | Unexpected or illegal meta frame control word block type. These signals indicate that an unexpected or illegal meta frame control word block type was detected. These signals can be used to collect the statistic RX_Bad_Control_Error as described in Table 5-9 of the Interlaken Protocol Definition, Revision 1.2. A value of 1 indicates an error in the corresponding lane. All bits are synced with c0_axi_clk. |
| stat_rx_descram_err[23:0] | c0_axi_clk | O | Scrambler state control word error. These signals indicate a mismatch between the received scrambler state word and the expected value. A value of 1 indicates an error in the corresponding lane. All bits are synced with c0_axi_clk. |
| stat_rx_mf_err[23:0] | c0_axi_clk | O | Meta frame synchronization word error. These signals indicate that an incorrectly formed meta frame synchronization word was detected in the respective lane. A value of 1 indicates an error occurred. All bits are synced with c0_axi_clk. |
| stat_rx_mf_len_err[23:0] | c0_axi_clk | O | Meta frame length error. These signals indicate whether a meta frame length mismatch occurred in the respective lane. A value of 1 indicates the corresponding lane is receiving meta frame of wrong length. All bits are synced with c0_axi_clk. |
| stat_rx_mf_repeat_err[23:0] | c0_axi_clk | O | Meta frame consecutive error. These signals indicate whether consecutive meta frame errors occurred in the respective lane. A value of 1 indicates an error in the corresponding lane. All bits are synced with c0_axi_clk. |
| stat_rx_crc32_valid[23:0] | c0_axi_clk | O | Diagnostic word CRC32 valid. This bus reflects
the validity of the CRC32 in the most recently received diagnostic
word for the respective lane. A value of 1 indicated the CRC32 was
valid and a value of 0 indicated the CRC32 was invalid. All bits are
synced with c0_axi_clk. Note: In Interlaken and FEC mode (where
CRC32 is not employed), these bits are not applicable and should
be ignored.
|
| stat_rx_crc32_err[23:0] | c0_axi_clk | O | Diagnostic word CRC32 error/invalid. This bus provides indication of an invalid CRC32 in the diagnostic word for the respective lane. These signals are asserted with a value of 1 for one AXI-S clock cycle each time an error is detected. All bits are synced with c0_axi_clk. |
| c0_stat_rx_err | c0_axi_clk | O | Control word error. This signal indicates whether a formatting error or a CRC24 error occurred in a control word. When operating in packet mode, this signal also indicates missing SOP or missing EOP errors. A value of 1 indicates an error occurred. Whenever this signal is asserted, all open packets are marked as containing errors as specified by the Interlaken Protocol Definition, Revision 1.2. By definition, there is no mechanism provided by Interlaken to associate a CRC24 or similar error with individual packets. This signal is asserted for one clock period each time an error is detected. |
| c0_stat_rx_msop_err | c0_axi_clk | O | Missing SOP error. This signal indicates that a missing SOP was detected (and corrected). |
| c0_stat_rx_meop_err | c0_axi_clk | O | Missing EOP error. This signal indicates that a missing EOP was detected (and corrected). |
| c0_stat_rx_burstmax_err | c0_axi_clk | O | RX BurstMax error. When this signal is a value of 1, a burst (that is, a sequence of data words between two control words) was detected that was longer than the value of BurstMax specified by c0_ctl_rx_burstmax. This signal is informational only and can be optionally ignored. |
| c0_stat_rx_burst_err | c0_axi_clk | O | RX burst error. This signal indicates that a BurstShort or a burst length error was detected. |
| c0_stat_rx_overflow_err | c0_axi_clk | O | RX FIFO overflow error. This signal indicates if the core clock for the ILKNF subsystem is too slow to properly receive the data being transmitted across the link. A value of 1 indicates an error occurred. In normal operation, this signal is always sampled as 0. If this signal is sampled as 1, the clocks are not set to proper frequencies and must be fixed. |
| stat_rx_diagword_lanestat[23:0] | c0_axi_clk | O | Lane status messaging outputs. This bus reflects the most recent
value in bit 33 of the diagnostic word received on the respective
lane. These bits should only be considered valid if the respective
bit in stat_rx_crc32_valid is a value of 1. All bits are synced with
c0_axi_clk. Note: In Interlaken and FEC mode (where
CRC32 is not employed), these bits are not 100% reliable as they
are susceptible to the post-FEC bit error rate
(BER).
|
| stat_rx_diagword_intfstat[23:0] | c0_axi_clk | O | Lane status messaging outputs. This bus reflects the most recent
value in bit 32 of the diagnostic word received on the respective
lane. These bits should only be considered valid if the respective
bit in stat_rx_crc32_valid is a value of 1. All bits are synced with
c0_axi_clk. Note: In Interlaken and FEC mode (where
CRC32 is not employed), these bits are not fully reliable
because they are susceptible to the post-FEC BER.
|
| c0_stat_rx_fc_stat[255:0] | c0_axi_clk | O | RX Flow control outputs. These signals indicate the flow control status for all of the calendar positions of the received data. A value of 1 means XON, a value of 0 means XOFF. These outputs reflect the information contained in bits 55-40 of the control words received by the RX. Only 256 in-band flow control bits are supported. If a longer calendar is received, latter bits are ignored and are never output. If a shorter calendar is received, the bits of c0_stat_rx_fc_stat that were not updated maintain their previous state. Each bit of c0_stat_rx_fc_stat represents a received flow control calendar entry. c0_stat_rx_fc_stat[0] is the first received calendar entry, c0_stat_rx_fc_stat[1] is the second received calendar entry, c0_stat_rx_fc_stat[2] is the third received calendar entry, etc. as explained in the example in section 5.3.4.1 of the Interlaken Protocol Definition, Revision 1.2. Whenever a CRC24 or a loss of lane alignment occurs, all bits of c0_stat_rx_fc_stat are set to a value of 0. |
| c0_stat_rx_mubits[7:0] | c0_axi_clk | O | RX multiple-use/general purpose control bits outputs. This bus contains the multi-use field of the Interlaken control (see the Interlaken Protocol Definition, Revision 1.2). The value of the bus represents bits[31:24] of the most recently received Interlaken control word. |
| c0_stat_rx_mubits_updated | c0_axi_clk | O | RX multiple-use/general purpose control bits updated outputs. This output indicates that c0_stat_rx_mubits has been updated and is asserted for one clock cycle. |
| Port | Clock Domain | I/O | Description |
|---|---|---|---|
| stat_rx_fec<N>_am_lock[3:0] | rx_alt_serdes_clk[0] | O | AM lock indicators for logical lanes of 100G RX FEC<N> when configured for Interlaken mode. Clocked by rx_alt_serdes_clk[0] regardless of the FEC instance. This signal is not valid in FEC-only mode. |
| stat_rx_fec<N>_aligned | rx_alt_serdes_clk[0]/rx_alt_serdes_clk[N] | O | 100G RX FEC<N> alignment status when configured for Interlaken mode. In FEC-only mode, this signal indicates that the FEC is ready to encode/decode codewords. |
| stat_rx_fec_lane_mapping_value[7:0] | apb3_clk | O | 100G RX FEC lane mapping of PMA lanes when configured for Interlaken mode. When stat_rx_lane_mapping_sync=1, the value on this bus indicates the mappings for FEC0 instance. The subsequent cycle shows the mappings for FEC1, and so on until FEC5 is reached. During each cycle, bits[7:6] hold the lane 3 mapping value, bits[5:4] hold the lane 2 mapping value, bits [3:2] hold the lane 1 mapping value, and bits[1:0] hold the lane 0 mapping value. This signal is not valid in FEC-only mode. |
| stat_rx_fec_lane_mapping_sync | apb3_clk | O | 100G RX FEC lane mapping sync signal. This signal is asserted every six clock cycles. |
| stat_rx_fec_lane_delay_value[14:0] | apb3_clk | O | 100G RX FEC alignment delay for PMA lane (in UIs). When stat_rx_lane_delay_sync=1, the value on this bus indicates the alignment delay for PMA lane 0 of FEC0 instance. The subsequent cycles show the alignment delay values for PMA lane 1, 2 and 3 of FEC0 instance. The next four cycles show the alignment delay for PMA lane 0, 1, 2, and 3 of FEC1, and so on. This signal is not valid in FEC-only mode. |
| stat_rx_fec_lane_delay_sync | apb3_clk | O | 100G RX FEC alignment delay sync signal. This signal is asserted every 24 clock cycles. |
| stat_rx_fec<N>_slice0_cw_inc | rx_alt_serdes_clk[0]/ rx_alt_serdes_clk[N] | O | Processed codeword count increment for FEC<N> 100G decoder when the corresponding RS-FEC instance is configured for Interlaken mode or 100G FEC-only mode. Processed codeword count increment for FEC<N> slice0 50G decoder when the corresponding RS-FEC instance is configured as two 50 Gb/s RS-FEC decoder/encoder pairs. |
| stat_rx_fec<N>_slice0_corrected_cw_inc | rx_alt_serdes_clk[0]/ rx_alt_serdes_clk[N] | O | Corrected codeword count increment for FEC<N> 100G decoder when the corresponding RS-FEC instance is configured for Interlaken mode or 100G FEC-only mode. Corrected codeword count increment for FEC<N> slice0 50G decoder when the corresponding RS-FEC instance is configured as two 50 Gb/s RS-FEC decoder/encoder pairs. |
| stat_rx_fec<N>_slice0_uncorrected_cw_inc | rx_alt_serdes_clk[0]/ rx_alt_serdes_clk[N] | O | Uncorrected codeword count increment for FEC<N> 100G decoder when the corresponding RS-FEC instance is configured for Interlaken mode or 100G FEC-only mode. Uncorrected codeword count increment for FEC<N> slice0 50G decoder when the corresponding RS-FEC instance is configured as two 50 Gb/s RS-FEC decoder/encoder pairs. |
| stat_rx_fec<N>_slice1_cw_inc | rx_alt_serdes_clk[0]/ rx_alt_serdes_clk[N] | O | Processed codeword count increment for FEC<N> 50G slice1 decoder. This signal is valid in FEC-only mode. It is not valid in Interlaken mode. In FEC-only mode, this signal is only valid when the corresponding RS-FEC instance is configured as two 50 Gb/s RS-FEC decoder/encoder pairs. |
| stat_rx_fec<N>_slice1_corrected_cw_inc | rx_alt_serdes_clk[0]/ rx_alt_serdes_clk[N] | O | Corrected codeword count increment for FEC<N> 50G slice1 decoder. This signal is valid in FEC-only mode. It is not valid in Interlaken mode. In FEC-only mode, this signal is only valid when the corresponding RS-FEC instance is configured as two 50 Gb/s RS-FEC decoder/encoder pairs. |
| stat_rx_fec<N>_slice1_uncorrected_cw_inc | rx_alt_serdes_clk[0]/ rx_alt_serdes_clk[N] | O | Uncorrected codeword count increment for FEC<N> 50G slice1 decoder. This signal is valid in FEC-only mode. It is not valid in Interlaken mode. In FEC-only mode, this signal is only valid when the corresponding RS-FEC instance is configured as two 50 Gb/s RS-FEC decoder/encoder pairs. |
| stat_rx_fec<N>_lane0_err_count_inc[3:0] | rx_alt_serdes_clk[0] /rx_alt_serdes_clk[N] | O | Symbol error count increment for lane0 of FEC<N> decoder. This signal is valid in both Interlaken and FEC-only mode. This bus is valid once per codeword. The value of the bus before and after the valid cycle is all zeros. In FEC-only mode, the total symbol error count for a codeword in 100G mode is the sum of error count on lane 0, lane 1, lane 2 and lane 3. Similarly, the total symbol error count of a codeword for 50G slice 0 is the sum of error count on lane 0 and lane 1. For slice 1, the total error count of a codeword in the sum of error count for lane 2 and lane 3. |
| stat_rx_fec<N>_lane1_err_count_inc[3:0] | rx_alt_serdes_clk[0]/ rx_alt_serdes_clk[N] | O | Symbol error count increment for lane1 of FEC<N> decoder. This signal is valid in both Interlaken and FEC-only mode. This bus is valid once per codeword. The value of the bus before and after the valid cycle is all zeros. |
| stat_rx_fec<N>_lane2_err_count_inc[3:0] | rx_alt_serdes_clk[0]/ rx_alt_serdes_clk[N] | O | Symbol error count increment for lane 2 of FEC<N> decoder. This signal is valid in both Interlaken and FEC-only mode. This bus is valid once per codeword. The value of the bus before and after the valid cycle is all zeros. |
| stat_rx_fec<N>_lane3_err_count_inc[3:0] | rx_alt_serdes_clk[0]/ rx_alt_serdes_clk[N] | O | Symbol error count increment for lane3 of FEC<N> decoder. This signal is valid in both Interlaken and FEC-only mode. This bus is valid once per codeword. The value of the bus before and after the valid cycle is all zeros. |
| stat_rx_fec<N>_lane0_err_0to1_inc[7:0] | rx_alt_serdes_clk[0]/ rx_alt_serdes_clk[N] | O | 0-to-1 error count increment for lane0 of FEC<N> decoder. This signal is valid in both Interlaken and FEC-only mode. This bus is valid once per codeword. The value of the bus before and after the valid cycle is all 0’s. In FEC-only mode, the total bit error (0 to 1) count for a codeword in 100G mode is the sum of bit error count on lane 0, lane 1, lane 2 and lane 3. Similarly, the total bit error count of a codeword for 50G slice 0 is the sum of error count on lane 0 and lane 1. For slice 1, the total bit error count of a codeword in the sum of bit error count for lane 2 and lane 3. |
| stat_rx_fec<N>_lane1_err_0to1_inc[7:0] | rx_alt_serdes_clk[0]/ rx_alt_serdes_clk[N] | O | 0-to-1 error count increment for lane1 of FEC<N> decoder. This signal is valid in both Interlaken and FEC-only mode. This bus is valid once per codeword. The value of the bus before and after the valid cycle is all zeros. |
| stat_rx_fec<N>_lane2_err_0to1_inc[7:0] | rx_alt_serdes_clk[0]/ rx_alt_serdes_clk[N] | O | 0-to-1 error count increment for lane 2 of FEC<N> decoder. This signal is valid in both Interlaken and FEC-only mode. This bus is valid once per codeword. The value of the bus before and after the valid cycle is all zeros. |
| stat_rx_fec<N>_lane3_err_0to1_inc[7:0] | rx_alt_serdes_clk[0]/ rx_alt_serdes_clk[N] | O | 0-to-1 error count increment for lane 3 of FEC<N> decoder. This signal is valid in both Interlaken and FEC-only mode. This bus is valid once per codeword. The value of the bus before and after the valid cycle is all 0’s. |
| stat_rx_fec<N>_lane0_err_1to0_inc[7:0] | rx_alt_serdes_clk[0]/ rx_alt_serdes_clk[N] | O | 1-to-0 error count increment for lane 0 of FEC<N> decoder. This signal is valid in both Interlaken and FEC-only mode. This bus is valid once per codeword. The value of the bus before and after the valid cycle is all zeros. In FEC-only mode, the total bit error (1 to 0) count for a codeword in 100G mode is the sum of bit error count on lane 0, lane 1, lane 2 and lane 3. Similarly, the total bit error count of a codeword for 50G slice 0 is the sum of bit error count on lane 0 and lane 1. For slice 1, the total bit error count of a codeword in the sum of bit error count for lane 2 and lane 3. |
| stat_rx_fec<N>_lane1_err_1to0_inc[7:0] | rx_alt_serdes_clk[0]/ rx_alt_serdes_clk[N] | O | 1-to-0 error count increment for lane1 of FEC<N> decoder. This signal is valid in both Interlaken and FEC-only mode. This bus is valid once per codeword. The value of the bus before and after the valid cycle is all zeros. |
| stat_rx_fec<N>_lane2_err_1to0_inc[7:0] | rx_alt_serdes_clk[0]/ rx_alt_serdes_clk[N] | O | 1-to-0 error count increment for lane2 of FEC<N> decoder. This signal is valid in both Interlaken and FEC-only mode. This bus is valid once per codeword. The value of the bus before and after the valid cycle is all zeros. |
| stat_rx_fec<N>_lane3_err_1to0_inc[7:0] | rx_alt_serdes_clk[0]/ rx_alt_serdes_clk[N] | O | 1-to-0 error count increment for lane3 of FEC<N> decoder. This signal is valid in both Interlaken and FEC-only mode. This bus is valid once per codeword. The value of the bus before and after the valid cycle is all zeros. |
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