This section describes the FEC-only interface. The following tables define the description, direction, and meaning of the various signals.
Note: In the tables, <N> is the FEC instance number 0 to 5.
| Port Name | Clock Domain | I/O | Description |
|---|---|---|---|
| tx_fec<N>_slice0_din[159:0] | tx_alt_serdes_clk[<N>] | I | Input data for slice0 of FEC<N> TX encoder in FEC-only mode. |
| tx_fec<N>_slice1_din[159:0] | tx_alt_serdes_clk[<N>] | I | Input data for slice1 of FEC<N> TX encoder in FEC-only mode. |
| tx_fec<N>_slice0_din_start | tx_alt_serdes_clk[<N>] | I | Start of codeword on tx_fec<N>_slice0_din in FEC-only mode. |
| tx_fec<N>_slice1_din_start | tx_alt_serdes_clk[<N>] | I | Start of codeword on tx_fec<N>_slice1_din in FEC-only mode. This signal is ignored when FEC<N> is configured in 100G FEC-only mode. |
| tx_serdes_data0[79:0] | tx_alt_serdes_clk[0] | O | In FEC-only mode, this contains the FEC-encoded data output. |
| tx_serdes_data1[79:0] | tx_alt_serdes_clk[0] | O | In FEC-only mode, this contains the FEC-encoded data output. |
| tx_serdes_data2[79:0] | tx_alt_serdes_clk[0] | O | In FEC-only mode, this contains the FEC-encoded data output. |
| tx_serdes_data3[79:0] | tx_alt_serdes_clk[0] | O | In FEC-only mode, this contains the FEC-encoded data output. |
| tx_serdes_data4[79:0] | tx_alt_serdes_clk[1] | O | In FEC-only mode, this contains the FEC-encoded data output. |
| tx_serdes_data5[79:0] | tx_alt_serdes_clk[1] | O | In FEC-only mode, this contains the FEC-encoded data output. |
| tx_serdes_data6[79:0] | tx_alt_serdes_clk[1] | O | In FEC-only mode, this contains the FEC-encoded data output. |
| tx_serdes_data7[79:0] | tx_alt_serdes_clk[1] | O | In FEC-only mode, this contains the FEC-encoded data output. |
| tx_serdes_data8[79:0] | tx_alt_serdes_clk[2] | O | In FEC-only mode, this contains the FEC-encoded data output. |
| tx_serdes_data9[79:0] | tx_alt_serdes_clk[2] | O | In FEC-only mode, this contains the FEC-encoded data output. |
| tx_serdes_data10[79:0] | tx_alt_serdes_clk[2] | O | In FEC-only mode, this contains the FEC-encoded data output. |
| tx_serdes_data11[79:0] | tx_alt_serdes_clk[2] | O | In FEC-only mode, this contains the FEC-encoded data output. |
| tx_serdes_data12[79:0] | tx_alt_serdes_clk[3] | O | In FEC-only mode, this contains the FEC-encoded data output. |
| tx_serdes_data13[79:0] | tx_alt_serdes_clk[3] | O | In FEC-only mode, this contains the FEC-encoded data output. |
| tx_serdes_data14[79:0] | tx_alt_serdes_clk[3] | O | In FEC-only mode, this contains the FEC-encoded data output. |
| tx_serdes_data15[79:0] | tx_alt_serdes_clk[3] | O | In FEC-only mode, this contains the FEC-encoded data output. |
| tx_serdes_data16[79:0] | tx_alt_serdes_clk[4] | O | In FEC-only mode, this contains the FEC-encoded data output. |
| tx_serdes_data17[79:0] | tx_alt_serdes_clk[4] | O | In FEC-only mode, this contains the FEC-encoded data output. |
| tx_serdes_data18[79:0] | tx_alt_serdes_clk[4] | O | In FEC-only mode, this contains the FEC-encoded data output. |
| tx_serdes_data19[79:0] | tx_alt_serdes_clk[4] | O | In FEC-only mode, this contains the FEC-encoded data output. |
| tx_serdes_data20[79:0] | tx_alt_serdes_clk[5] | O | In FEC-only mode, this contains the FEC-encoded data output. |
| tx_serdes_data21[79:0] | tx_alt_serdes_clk[5] | O | In FEC-only mode, this contains the FEC-encoded data output. |
| tx_serdes_data22[79:0] | tx_alt_serdes_clk[5] | O | In FEC-only mode, this contains the FEC-encoded data output. |
| tx_serdes_data23[79:0] | tx_alt_serdes_clk[5] | O | In FEC-only mode, this contains the FEC-encoded data output. |
| tx_fec0_slice0_dout_start | tx_alt_serdes_clk[0] | O | When FEC0 is configured for 100G or 50G FEC-only mode, indicates start of codeword on tx_serdes_data0. |
| tx_fec0_slice1_dout_start | tx_alt_serdes_clk[0] | O | When FEC0 is configured for 50G FEC-only mode, indicates start of codeword on tx_serdes_data2. When FEC0 is configured for 100G FEC-only mode, this signal mimics its slice0 counterpart and can be ignored. |
| tx_fec1_slice0_dout_start | tx_alt_serdes_clk[1] | O | When FEC1 is configured for 100G or 50G FEC-only mode, indicates start of codeword on tx_serdes_data4. |
| tx_fec1_slice1_dout_start | tx_alt_serdes_clk[1] | O | When FEC1 is configured for 50G FEC-only mode, indicates start of codeword on tx_serdes_data6. When FEC1 is configured for 100G FEC-only mode, this signal mimics its slice0 counterpart and can be ignored. |
| tx_fec2_slice0_dout_start | tx_alt_serdes_clk[2] | O | When FEC2 is configured for 100G or 50G FEC-only mode, indicates start of codeword on tx_serdes_data8. |
| tx_fec2_slice1_dout_start | tx_alt_serdes_clk[2] | O | When FEC2 is configured for 50G FEC-only mode, indicates start of codeword on tx_serdes_data10. When FEC2 is configured for 100G FEC-only mode, this signal mimics its slice0 counterpart and can be ignored. |
| tx_fec3_slice0_dout_start | tx_alt_serdes_clk[3] | O | When FEC3 is configured for 100G or 50G FEC-only mode, indicates start of codeword on tx_serdes_data12. |
| tx_fec3_slice1_dout_start | tx_alt_serdes_clk[3] | O | When FEC3 is configured for 50G FEC-only mode, indicates start of codeword on tx_serdes_data14. When FEC3 is configured for 100G FEC-only mode, this signal mimics its slice0 counterpart and can be ignored. |
| tx_fec4_slice0_dout_start | tx_alt_serdes_clk[4] | O | When FEC4 is configured for 100G or 50G FEC-only mode, indicates start of codeword on tx_serdes_data16. |
| tx_fec4_slice1_dout_start | tx_alt_serdes_clk[4] | O | When FEC4 is configured for 50G FEC-only mode, indicates start of codeword on tx_serdes_data18. When FEC4 is configured for 100G FEC-only mode, this signal mimics its slice0 counterpart and can be ignored. |
| tx_fec5_slice0_dout_start | tx_alt_serdes_clk[5] | O | When FEC5 is configured for 100G or 50G FEC-only mode, indicates start of codeword on tx_serdes_data20. |
| tx_fec5_slice1_dout_start | tx_alt_serdes_clk[5] | O | When FEC5 is configured for 50G FEC-only mode, indicates start of codeword on tx_serdes_data22. When FEC5 is configured for 100G FEC-only mode, this signal mimics its slice0 counterpart and can be ignored. |
| Port Name | Clock Domain | I/O | Description |
|---|---|---|---|
| rx_serdes_data0[79:0] | rx_alt_serdes_clk[0] | O | In FEC-only mode, this contains the FEC-encoded data input. |
| rx_serdes_data1[79:0] | rx_alt_serdes_clk[0] | O | In FEC-only mode, this contains the FEC-encoded data input. |
| rx_serdes_data2[79:0] | rx_alt_serdes_clk[0] | O | In FEC-only mode, this contains the FEC-encoded data input. |
| rx_serdes_data3[79:0] | rx_alt_serdes_clk[0] | O | In FEC-only mode, this contains the FEC-encoded data input. |
| rx_serdes_data4[79:0] | rx_alt_serdes_clk[1] | O | In FEC-only mode, this contains the FEC-encoded data input. |
| rx_serdes_data5[79:0] | rx_alt_serdes_clk[1] | O | In FEC-only mode, this contains the FEC-encoded data input. |
| rx_serdes_data6[79:0] | rx_alt_serdes_clk[1] | O | In FEC-only mode, this contains the FEC-encoded data input. |
| rx_serdes_data7[79:0] | rx_alt_serdes_clk[1] | O | In FEC-only mode, this contains the FEC-encoded data input. |
| rx_serdes_data8[79:0] | rx_alt_serdes_clk[2] | O | In FEC-only mode, this contains the FEC-encoded data input. |
| rx_serdes_data9[79:0] | rx_alt_serdes_clk[2] | O | In FEC-only mode, this contains the FEC-encoded data input. |
| rx_serdes_data10[79:0] | rx_alt_serdes_clk[2] | O | In FEC-only mode, this contains the FEC-encoded data input. |
| rx_serdes_data11[79:0] | rx_alt_serdes_clk[2] | O | In FEC-only mode, this contains the FEC-encoded data input. |
| rx_serdes_data12[79:0] | rx_alt_serdes_clk[3] | O | In FEC-only mode, this contains the FEC-encoded data input. |
| rx_serdes_data13[79:0] | rx_alt_serdes_clk[3] | O | In FEC-only mode, this contains the FEC-encoded data input. |
| rx_serdes_data14[79:0] | rx_alt_serdes_clk[3] | O | In FEC-only mode, this contains the FEC-encoded data input. |
| rx_serdes_data15[79:0] | rx_alt_serdes_clk[3] | O | In FEC-only mode, this contains the FEC-encoded data input. |
| rx_serdes_data16[79:0] | rx_alt_serdes_clk[4] | O | In FEC-only mode, this contains the FEC-encoded data input. |
| rx_serdes_data17[79:0] | rx_alt_serdes_clk[4] | O | In FEC-only mode, this contains the FEC-encoded data input. |
| rx_serdes_data18[79:0] | rx_alt_serdes_clk[4] | O | In FEC-only mode, this contains the FEC-encoded data input. |
| rx_serdes_data19[79:0] | rx_alt_serdes_clk[4] | O | In FEC-only mode, this contains the FEC-encoded data input. |
| rx_serdes_data20[79:0] | rx_alt_serdes_clk[5] | O | In FEC-only mode, this contains the FEC-encoded data input. |
| rx_serdes_data21[79:0] | rx_alt_serdes_clk[5] | O | In FEC-only mode, this contains the FEC-encoded data input. |
| rx_serdes_data22[79:0] | rx_alt_serdes_clk[5] | O | In FEC-only mode, this contains the FEC-encoded data input. |
| rx_serdes_data23[79:0] | rx_alt_serdes_clk[5] | O | In FEC-only mode, this contains the FEC-encoded data input. |
| rx_fec0_slice0_din_start | rx_alt_serdes_clk[0] | I | Start of codeword on rx_serdes_data0 in 100G or 50G FEC-only mode. |
| rx_fec0_slice1_din_start | rx_alt_serdes_clk[0] | I | Start of codeword on rx_serdes_data2 in 50G FEC-only mode. This signal is ignored when FEC0 is configured in 100G FEC-only mode. |
| rx_fec1_slice0_din_start | rx_alt_serdes_clk[1] | I | Start of codeword on rx_serdes_data4 in 100G or 50G FEC-only mode. |
| rx_fec1_slice1_din_start | rx_alt_serdes_clk[1] | I | Start of codeword on rx_serdes_data6 in 50G FEC-only mode. This signal is ignored when FEC1 is configured in 100G FEC-only mode. |
| rx_fec2_slice0_din_start | rx_alt_serdes_clk[2] | I | Start of codeword on rx_serdes_data8 in 100G or 50G FEC-only mode. |
| rx_fec2_slice1_din_start | rx_alt_serdes_clk[2] | I | Start of codeword on rx_serdes_data10 in 50G FEC-only mode. This signal is ignored when FEC2 is configured in 100G FEC-only mode. |
| rx_fec3_slice0_din_start | rx_alt_serdes_clk[3] | I | Start of codeword on rx_serdes_data12 in 100G or 50G FEC-only mode. |
| rx_fec3_slice1_din_start | rx_alt_serdes_clk[3] | I | Start of codeword on rx_serdes_data14 in 50G FEC-only mode. This signal is ignored when FEC3 is configured in 100G FEC-only mode. |
| rx_fec4_slice0_din_start | rx_alt_serdes_clk[4] | I | Start of codeword on rx_serdes_data16 in 100G or 50G FEC-only mode. |
| rx_fec4_slice1_din_start | rx_alt_serdes_clk[4] | I | Start of codeword on rx_serdes_data18 in 50G FEC-only mode. This signal is ignored when FEC4 is configured in 100G FEC-only mode. |
| rx_fec5_slice0_din_start | rx_alt_serdes_clk[5] | I | Start of codeword on rx_serdes_data20 in 100G or 50G FEC-only mode. |
| rx_fec5_slice1_din_start | rx_alt_serdes_clk[5] | I | Start of codeword on rx_serdes_data22 in 50G FEC-only mode. This signal is ignored when FEC5 is configured in 100G FEC-only mode. |
| rx_fec<N>_slice0_dout[159:0] | rx_alt_serdes_clk[<N>] | O | Output data for slice0 of FEC<N> RX decoder in FEC-only mode. |
| rx_fec<N>_slice1_dout[159:0] | rx_alt_serdes_clk[<N>] | O | Output data for slice1 of FEC<N> RX decoder in FEC-only mode. |
| rx_fec<N>_slice0_dout_start | rx_alt_serdes_clk[<N>] | O | Start of codeword on rx_fec<N>_slice0_dout in 100G or 50G FEC-only mode. |
| rx_fec<N>_slice1_dout_start | rx_alt_serdes_clk[<N>] | O | Start of codeword on rx_fec<N>_slice1_dout in 50G FEC-only mode. When FEC<N> is configured for 100G FEC-only mode, this signal mimics its slice0 counterpart and can be ignored. |
| rx_fec<N>_slice0_dout_flags[3:0] | rx_alt_serdes_clk[<N>] | O | Decoder flag bits for slice0 of FEC<N> indicating the status of data on
rx_fec<N>_slice0_dout. bit[0] indicates that syndromes were clean (codeword had no errors) bit[1] indicates that syndromes were dirty (codeword had some errors) bit[2] indicates that decoder passed (codeword did not have uncorrectable errors) bit[3] indicates that decoder failed (codeword had uncorrectable errors) This signal is only valid in FEC-only mode. |
| rx_fec<N>_slice1_dout_flags[3:0] | rx_alt_serdes_clk[<N>] | O | Decoder flag bits for slice1 of FEC<N> indicating the status of data on
rx_fec<N>_slice1_dout. bit[0] indicates that syndromes were clean (codeword had no errors) bit[1] indicates that syndromes were dirty (codeword had some errors) bit[2] indicates that decoder passed (codeword did not have uncorrectable errors) bit[3] indicates that decoder failed (codeword had uncorrectable errors) This signal is only valid in FEC-only mode. This signal should be ignored when FEC<N> is configured in 100G mode. |