The packet generator and monitor generates packets for the segmented AXI4-Stream user interface and verifies them.
The packet generator consists of multiple segments depending on the width of the user interface. Each segment is 128-bit wide and contains a PRBS generator accompanied by a RAM with 256 entries. The RAM holds the values of ena, sop, eop, err, bctl, chan, and mty signals to be generated with the data on each clock edge for that segment. The user can write to each entry of the RAM through AXI4-Lite interface.
The generator calculates the statistics such as data checksum, channel sum, byte count, SOP count, EOP count, and error count for the transmitted packets, and the monitor calculates them for the received packets. You can access these statistics through AXI4-Lite interface.