|
Subystem Specifics |
| Supported Device Family
1
|
Versal architecture |
| Supported User Interfaces |
Segmented AXI4-Stream,
AXI4-Lite
|
| Resources |
|
| Provided with
Subystem
|
| Design Files |
Encrypted RTL |
| Example Design |
Verilog |
| Test Bench |
Verilog |
| Constraints File |
Xilinx Design Constraints (XDC) |
| Simulation Model |
Verilog |
| Supported S/W Driver |
N/A |
| Tested Design
Flows
2
|
| Design Entry |
Vivado® Design Suite
|
| Simulation |
For supported simulators, see the Xilinx Design Tools: Release Notes
Guide. |
| Synthesis |
Synopsys or Vivado synthesis |
| Support |
| Release Notes and Known Issues |
N/A |
| All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775
|
|
Xilinx
Support web page
|
- For a complete list of supported devices, see the
Vivado®
IP catalog.
- For the supported versions of third-party
tools, see the Xilinx Design Tools: Release Notes
Guide.
|