Reduced Fabric Clock Frequency with Low Latency

Reduced Fabric Clock Frequency with Low Latency - 1.1 English

Versal ACAP Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)

Document ID

PG371

Release Date

2022-07-21

Version

1.1 English

To minimize the core latency, you might choose to run the ILKNF subsystem with a faster core clock (compared with the same corresponding configuration found in the previous section). In that case, the values in the c0_ctl_rx_rate_adapt_inc[7:0] and c0_ctl_rx_rate_adapt_dec[7:0] register fields must be set appropriately according to the following table.

Table 1. Rate Adapter Inc/Dec Values for Low-Latency Core Clock Interlaken Configurations
Maximum Transceiver Rate (Gb/s)	Max # Lanes	Aggregate BW (Gb/s)	AXI Width (bits)	AXI Clock (MHz)	Core Clock (MHz)	GT I/F Width (bits)	RX Rate Adapt Inc¹	RX Rate Adapt Dec²
56.42	12	677.04	2048	331	662	160	32	16
	12	677.04	1536	441	662		24	16
	10	564.2	2048	276	662		32	13
	10	564.2	1536	368	662		24	13
	8	451.36	1536	294	662		24	10
	8	451.36	1024	441	662		16	10
	6	338.52	1024	331	662		16	8
	6	338.52	768	441	662		12	8
	4	225.68	768	294	662		12	5
	4	225.68	512	441	662		8	5
53.125	12	637.5	2048	312	624	80	32	16
	12	637.5	1536	416	624		24	16
	10	531.25	2048	260	624		32	13
	10	531.25	1536	347	624		24	13
	8	425	1536	278	624		24	10
	8	425	1024	416	624		16	10
	6	318.75	1024	312	624		16	8
	6	318.75	768	416	624		12	8
	4	212.5	768	278	624		12	5
	4	212.5	512	416	624		8	5
28.21	24	677.04	2048	331	662	80	32	16
	24	677.04	1536	441	662		24	16
	18	507.78	2048	249	662		32	12
	18	507.78	1536	331	662		24	12
	16	451.36	1536	294	662		24	10
	16	451.36	1024	441	662		16	10
	12	338.52	1024	331	662		16	8
	12	338.52	768	441	662		12	8
	10	282.1	1024	277	662		16	6
	10	282.1	768	369	662		12	6
	8	225.68	768	294	662		12	5
	8	225.68	512	441	662		8	5
	6	169.26	512	331	662		8	4
25.78125	24	618.75	2048	303	624	40	32	15
	24	618.75	1536	404	624		24	15
	18	464.0625	2048	228	624		32	11
	18	464.0625	1536	303	624		24	11
	16	412.5	1536	269	624		24	10
	16	412.5	1024	403	624		16	10
	12	309.375	1024	303	624		16	7
	12	309.375	768	404	624		12	7
	10	257.8125	1024	253	624		16	6
	10	257.8125	768	337	624		12	6
	8	206.25	768	269	624		12	5
	8	206.25	512	403	624		8	5
	6	154.6875	512	303	624		8	3
12.5	24	300	1024	293	662	40	16	7
	24	300	768	391	662		12	7
	18	225	768	293	662		12	5
	12	150	512	293	662		8	3
This column refers to the `c0_ctl_rx_rate_adapt_inc[3:0]` field of the CFG_C0_RX_RATE_ADAPT_INC register. This column refers to the `c0_ctl_rx_rate_adapt_dec[3:0]` field of the CFG_C0_RX_RATE_ADAPT_DEC register.