The following examples illustrate segmented AXI4-Stream cycles covering various combinations of SOP, DAT (data in the middle of a packet), EOP, and IDLE (no data on the bus).
In the first two examples below, the segmented AXI4-Stream bus is assumed to be 512 bits wide and each segment is 128 bits wide (16 bytes). The TX direction is illustrated. The RX direction has analogous behavior. Unlike the TX, the RX is able to transfer more packets in one cycle, for example, with two SOP and two EOP, due to the removal of overhead and no requirement to meet BurstShort.
The following tables show many possible TX segmented AXI4-Stream bus cycles. In these examples, BurstMax has been set to 256 and BurstShort to 64. The different shadings represent different bursts from different packets.
The numbers in parenthesis are used to identify the segments that correspond to the same packet.
| Clock Cycle | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 |
|---|---|---|---|---|---|---|---|---|---|---|
| seg0 | SOP(0) | IDLE | SOP(1) | SOP(2) | DAT(2) | DAT(3) | IDLE | DAT(3) | SOP(4) | IDLE |
| seg1 | DAT(0) | IDLE | DAT(1) | DAT(2) | EOP(2) | DAT(3) | IDLE | DAT(3) | DAT(4) | IDLE |
| seg2 | DAT(0) | IDLE | DAT(1) | DAT(2) | SOP(3) | DAT(3) | IDLE | DAT(3) | DAT(4) | IDLE |
| seg3 | EOP(0) | IDLE | EOP(1) | DAT(2) | DAT(3) | DAT(3) | IDLE | EOP(3) | DAT(4) | IDLE |
| c0_tx_rdyout | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 |
| c0_tx_ovfout | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Clock Cycle | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 |
|---|---|---|---|---|---|---|---|---|---|---|
| seg0 | DAT(0) | DAT(0) | DAT(0) | DAT(0) | DAT(1) | DAT(1) | DAT(1) | DAT(0) | SOP(2) | IDLE |
| seg1 | DAT(0) | DAT(0) | DAT(0) | DAT(1) | DAT(1) | DAT(1) | IDLE | DAT(0) | DAT(2) | IDLE |
| seg2 | DAT(0) | DAT(0) | DAT(0) | DAT(1) | DAT(1) | DAT(1) | IDLE | DAT(0) | DAT(2) | IDLE |
| seg3 | DAT(0) | DAT(0) | DAT(0) | DAT(1) | DAT(1) | DAT(1) | IDLE | EOP(0) | DAT(2) | IDLE |
| c0_tx_rdyout | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 |
| c0_tx_ovfout | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
The Interlaken Protocol Definition, Revision 1.2, describes an enhanced scheduling algorithm. The previous example is the same as a scheduler with the enhanced algorithm that has a BurstMin of 64-bytes.
Following are examples for a 2048-bit TX AXI4-Stream bus with 16 segments of 16 bytes each.
| Clock Cycle | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 |
|---|---|---|---|---|---|---|---|---|---|---|
| seg0 | DAT(0) | DAT(2) | DAT(4) | DAT(5) | SOP(6) | IDLE | DAT(6) | DAT(7) | SOP(9) | IDLE |
| seg1 | DAT(0) | EOP(2) | DAT(4) | DAT(5) | DAT(6) | IDLE | DAT(6) | DAT(7) | DAT(9) | IDLE |
| seg2 | DAT(0) | SOPEOP(3) | DAT(4) | DAT(5) | DAT(6) | IDLE | DAT(6) | DAT(7) | DAT(9) | IDLE |
| seg3 | DAT(0) | IDLE | DAT(4) | DAT(5) | DAT(6) | IDLE | DAT(6) | DAT(7) | EOP(9) | IDLE |
| seg4 | DAT(0) | IDLE | DAT(4) | DAT(5) | DAT(6) | IDLE | DAT(6) | DAT(7) | SOP(10) | IDLE |
| seg5 | DAT(0) | IDLE | DAT(4) | DAT(5) | DAT(6) | IDLE | DAT(6) | EOP(7) | DAT(10) | IDLE |
| seg6 | DAT(0) | SOP(4) | DAT(4) | EOP(5) | DAT(6) | IDLE | DAT(6) | SOP(8) | EOP(10) | IDLE |
| seg7 | DAT(0) | DAT(4) | DAT(4) | IDLE | DAT(6) | IDLE | DAT(6) | DAT(8) | IDLE | IDLE |
| seg8 | DAT(0) | DAT(4) | EOP(4) | IDLE | DAT(6) | IDLE | DAT(6) | DAT(8) | SOP(11) | IDLE |
| seg9 | EOP(0) | DAT(4) | SOP(5) | IDLE | DAT(6) | IDLE | DAT(6) | DAT(8) | EOP(11) | IDLE |
| seg10 | SOP(1) | DAT(4) | DAT(5) | IDLE | DAT(6) | IDLE | EOP(6) | DAT(8) | IDLE | IDLE |
| seg11 | DAT(1) | DAT(4) | DAT(5) | IDLE | DAT(6) | IDLE | SOP(7) | DAT(8) | IDLE | IDLE |
| seg12 | EOP(1) | DAT(4) | DAT(5) | IDLE | DAT(6) | IDLE | DAT(7) | DAT(8) | SOPEOP(12) | IDLE |
| seg13 | IDLE | DAT(4) | DAT(5) | IDLE | DAT(6) | IDLE | DAT(7) | EOP(8) | IDLE | IDLE |
| seg14 | SOP(2) | DAT(4) | DAT(5) | IDLE | DAT(6) | IDLE | DAT(7) | IDLE | IDLE | IDLE |
| seg15 | DAT(2) | DAT(4) | DAT(5) | IDLE | DAT(6) | IDLE | DAT(7) | IDLE | IDLE | IDLE |
| tx_rdyout | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
| tx_ovfout | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Note: In the previous table:
- Cycle 1
- Segment 13 is IDLE in order for the 48-byte packet on segments 10-12 to meet the 64-byte BurstShort requirement on the Interlaken interface.
- Cycle 2
- Segment 2 is a packet ≤ 16 bytes with both start of packet and end of packet; it is followed by three IDLEs to meet the 64-byte BurstShort requirement on the Interlaken interface.
- Cycle 4
- Segment 7-15 are IDLEs following an EOP segment. Same in cycle 8, starting with segment 14.
- Cycle 6
- All segments are IDLE in response to TX backpressure signaled on
c0_tx_rdyout. - Cycle 9
- Four small packets are transferred in one cycle. Depending on how many 16-byte segments they fill, they need to be padded with IDLE segments to the 64-byte BurstShort value.
| Clock Cycle | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 |
|---|---|---|---|---|---|---|---|---|---|---|---|
| seg0 | SOP(0) | SOP(1) | DAT(1) | DAT(2) | DAT(4) | DAT(6) | DAT(6) | SOP(9) | DAT(10) | DAT(11) | IDLE |
| seg1 | DAT(0) | DAT(1) | DAT(1) | DAT(2) | DAT(4) | DAT(6) | DAT(6) | EOP(9) | DAT(10) | EOP(11) | IDLE |
| seg2 | DAT(0) | DAT(1) | DAT(1) | DAT(2) | EOP(4) | DAT(6) | DAT(6) | IDLE | DAT(10) | DAT(10) | IDLE |
| seg3 | DAT(0) | DAT(1) | DAT(1) | EOP(2) | SOPEOP(5) | DAT(6) | DAT(6) | IDLE | DAT(10) | DAT(10) | IDLE |
| seg4 | DAT(0) | DAT(1) | DAT(1) | SOP(3) | IDLE | DAT(6) | DAT(6) | SOP(10) | SOP(11) | DAT(10) | IDLE |
| seg5 | DAT(0) | DAT(1) | DAT(1) | DAT(3) | IDLE | DAT(6) | DAT(6) | DAT(10) | DAT(11) | DAT(10) | IDLE |
| seg6 | DAT(0) | DAT(1) | EOP(1) | DAT(3) | IDLE | DAT(6) | DAT(6) | DAT(10) | DAT(11) | DAT(10) | IDLE |
| seg7 | DAT(0) | DAT(1) | DAT(0) | EOP(3) | SOP(6) | SOP(7) | DAT(6) | DAT(10) | DAT(11) | DAT(10) | IDLE |
| seg8 | DAT(0) | DAT(1) | DAT(0) | SOP(4) | DAT(6) | DAT(7) | DAT(6) | DAT(10) | DAT(11) | DAT(10) | IDLE |
| seg9 | DAT(0) | DAT(1) | DAT(0) | DAT(4) | DAT(6) | DAT(7) | EOP(6) | DAT(10) | DAT(11) | DAT(10) | IDLE |
| seg10 | DAT(0) | DAT(1) | DAT(0) | DAT(4) | DAT(6) | EOP(7) | IDLE | DAT(10) | DAT(11) | DAT(10) | IDLE |
| seg11 | DAT(0) | DAT(1) | DAT(0) | DAT(4) | DAT(6) | SOP(8) | IDLE | DAT(10) | DAT(11) | DAT(10) | IDLE |
| seg12 | DAT(0) | DAT(1) | DAT(0) | DAT(4) | DAT(6) | DAT(8) | IDLE | DAT(10) | DAT(11) | DAT(10) | IDLE |
| seg13 | DAT(0) | DAT(1) | DAT(0) | DAT(4) | DAT(6) | EOP(8) | IDLE | DAT(10) | DAT(11) | DAT(10) | IDLE |
| seg14 | DAT(0) | DAT(1) | EOP(0) | DAT(4) | DAT(6) | IDLE | IDLE | DAT(10) | DAT(11) | DAT(10) | IDLE |
| seg15 | DAT(0) | DAT(1) | SOP(2) | DAT(4) | DAT(6) | DAT(6) | IDLE | DAT(10) | DAT(11) | DAT(10) | IDLE |
| tx_rdyout | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
| tx_ovfout | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Note: In the previous table:
- Cycle 1
- Some of the packets in this example are shown burst-interleaved. For example, the packet started in cycle 1 has a burst of 256 bytes, and an EOP burst of 128 bytes in cycle 3. In between these two bursts, there is another packet transmitted, starting in cycle 2 and ending in segment 6 of cycle 3.
- Cycle 2
- Even in Burst Interleaved Mode, it is possible to transmit a packet non-interrupted, as seen for the packet started in this cycle.
- Cycle 5
- The same rules must be observed for packets under 48 bytes to avoid BurstShort violations on the Interlaken interface. In this case, segments 4-6 must be IDLEs.
- Cycle 11
- The AXI4-Stream TX interface needs to respond to backpressure signaled by c0_tx_rdyout and drive IDLEs on all segments.