Data is transferred in a segment on the TX interface when the
corresponding tx_axis_tuser_ena<M> is a value of
1. The TX interface buffers data and does not forward the data until it has a sufficient
quantity. Therefore, it is acceptable to have clock cycles in which none of the tx_axis_tuser_ena<M> signals are active. To transfer
data during a cycle, tx_axis_tuser_ena0 must be 1,
(that is, the first segment has to be valid). It is illegal to have tx_axis_tuser_ena0 equal to 0, and the enables for other
segments (tx_axis_tuser_ena<M>, where M>0) set
to 1.
Data is transferred in a segment on the RX interface when the
corresponding rx_axis_tuser_ena<M> is a value of
1. Similarly, the RX interface buffers data and does not forward it until it has a
sufficient quantity. Therefore, there will be clock cycles in which none of the rx_axis_tuser_ena<M> signals are active.