The following table lists the ILKNF reset pins along with the corresponding soft reset found in the CFG_C0_RESET_REG, CFG_TX_SERDES_RESET_REG and CFG_RX_SERDES_RESET_REG registers.
| ILKNF Reset Pin | Associated CFG_C0_RESET_REG CFG_TX_SERDES_RESET_REG CFG_RX_SERDES_RESET_REG Bits | Description |
|---|---|---|
| c0_tx_reset | c0_tx_reset | TX reset for the ILKNF subsystem. |
| c0_rx_reset | c0_rx_reset | RX reset for the ILKNF subsystem. |
| tx_serdes_reset[5:0] | tx_serdes_reset[5:0] | TX reset for Interlaken lane logic. In FEC-only mode, this resets the FEC encoder. |
| rx_serdes_reset[5:0] | rx_serdes_reset[5:0] | RX reset for Interlaken lane logic. In FEC-only mode, this resets the FEC decoder. |
| apb3_preset | Resets the AXI4-Lite port logic and status registers. |