GT Reset Control Ports - 1.1 English

Versal ACAP Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)
Document ID
PG371
Release Date
2022-07-21
Version
1.1 English
Table 1. GT Reset and Control Ports
Port Name I/O Description
gt_reset_all_in[23:0] I Reset input to GT Reset IP. Each bit initiates data path and PLL reset sequence on the corresponding GT lane. Applies to both TX and RX.
gt_reset_tx_datapath_in[23:0] I Reset input to GT Reset IP. Each bit initiates the TX data path reset sequence on the corresponding GT lane.
gt_reset_rx_datapath_in[23:0] I Reset input to GT Reset IP. Each bit initiates the RX data path reset sequence on the corresponding GT lane.
gt_tx_reset_done_out[23:0] O TX Reset Done output from the GT Reset IP.
gt_rx_reset_done_out[23:0] O RX Reset Done output from the GT Reset IP.

Clock and reset connection between ILKNF and GT is shown in the following figure.

Figure 1. ILKNF and GT Clock and Reset Architecture