Coplanarity and Etching of the Contact Surface Area

Designing Heatsinks and Thermal Solutions for Xilinx Devices (XAPP1377)

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It is important that the contact surface of the heatsink be parallel to the mating surface to ensure the best thermal performance, improve overall reliability, and to minimize the possibility of damage. When the surface of the heatsink is not parallel, the best case is that the TIM thickness is suboptimal over portions of the device. This compromises thermal performance and causes uneven cooling. If the heatsink is askew and there is enough uneven pressure applied to a small portion of the device contact area, it can cause lid deformity. In the case of lidless devices it can damage the die. For lidded or lidless devices, this should be avoided by ensuring in the design that the heatsink contact surface is parallel to the device plane. Check with the heatsink manufacturer to make sure the manufacturing process maintains this.

Traditionally, the heatsink contact surface is generally manufactured as a smooth plane. Xilinx recommends the use of an etched pattern to improve the overall thermal performance. The etched pattern should be controlled to have a coplanularity of 0.050 mm to achieve the best contact. This is especially beneficial for lidless devices but applicable to any Xilinx device. Using an etched pattern compared to a smooth plane offers several benefits:
  • It reduces the overall contact resistance to the device by allowing micro-bubbles in the TIM1.5 or TIM2 material a place to recede rather than pooling and creating larger voids in the TIM.
  • The TIM materials with metallic particles can allow for a thinner bond line thickness (BLT) by allowing larger particles to settle in the etching grooves creating a thinner and more uniform TIM thickness.
  • The etching pattern adds more surface area for the TIM material to touch further reducing contact resistance.
  • As the contact surfaces deflect due to thermal expansion over temperature, the etching region serves as a reserve for additional TIM allowing the TIM material to transfer between surfaces rather than create larger voids or leakage.

The amount of improvement varies depending on application. Xilinx has observed anywhere from 1°C to 5°C improvement using this technique, however, more improvement is possible in the case of larger TIM voids.

Figure 1. Xilinx Recommended Etching Pattern for Contact Surface of Heatsink