Method 1: Enable, Power Good, and Daisy Chaining

Daisy chaining is the first type of power sequencing discussed in this section. It is the most basic and cost-effective method of power sequencing, but it is also the least intelligent and has drawbacks. This method mostly does not support power-down sequencing, which is a requirement for AMD devices. As previously stated, not powering down in the correct sequence can result in unexpected behavior.

Important: However, if the system is not writing to memory or communicating via the I/Os, all rails can be powered down at once.

Note: If this method is used, it is important that the power-down does not violate AMD guidelines. See Answer Record 76259 for more information.

Daisy chaining is implemented by using the enable (EN) and power good (PG) signal pins that are on VRMs by signaling to the next VRM in the sequence to power on directly or in a daisy chain pattern. The EN pin is an input to control the circuitry of a VRM that signals to enable the VRM output when pulled active-High/Low. The PG pin is an output signal from the VRM’s control circuitry that indicates the regulator is regulating in the correct voltage range and operating in its intended manner. By connecting the PG pins to the EN pin of the next VRM in the sequence, a sequence is created that waits for the previous rail in the sequence to power up.

The readback of this sequence can be achieved using two GPIOs as part of a Versal device design to initiate the sequence and read back that the last regulator in the sequence is powered correctly. This method can determine when all regulators have been brought up successfully, but cannot determine which regulator is not operating correctly. Also, it does not allow for power management as it has only two states, powered on or powered off completely.

The following figure illustrates the daisy chain topology.

Figure 1. Daisy Chain Topology

The first VRM requires a GPIO or a similar method of signaling the first VRM to power up and begin the daisy chain sequence. The logic threshold values and the turn-on times of the regulators are available in their respective data sheets, which should be taken into account when working out timings as there could be incompatibilities and some regulators can offer soft-start capability. To ensure that the signal driving the EN pin is capable of meeting the pin threshold requirements, a level shifter might be necessary between the activating signal and the EN pin to meet the threshold requirements (see the following figure). The PG and EN signals can be active-High or active-Low depending on the VRM. The control can be implemented by an external controller, Versal device I/Os, or power-on. There are multiple variations to sequencing using the EN and PG signals. This method can be modified to meet your applications requirements as you see fit.

If your GPIO voltage level is not compatible with the VRM Enable pins, a level shifter can be used to step up or down the voltage to the required level. An example of this is illustrated in the following figure.

Figure 2. Level Shifter

If the VRM does not have a soft-start feature, an RC delay element can be added to delay the enabling of regulators when using this method. See Figure 1 for an example of how the RC delay circuit can be added to a VRM ramp up. When calculating the delays, the VRM turn-on time should be relative to the previous delay implemented on the previous regulator (td3 > td2 > td1).

The delay in the EN pin can be calculated with the following equation.

In this equation, td is the time delay in ms, R is the resistor value in KΩ, C is the capacitor value in µF, VIN is the voltage of the EN signal, and VthEN is the threshold value of the EN pin.

Note: A VRM data sheet might have a different calculation. Contact your power vendor to confirm that this equation is applicable to your VRM.

There are multiple variations to sequencing using the EN and PG signals. This method can be modified to meet your application's requirements.