Power-down Sequencing

Simplified Power Sequencing (XAPP1375)

Document ID
Release Date
1.1 English

Power-down sequencing is just as important a requirement for AMD devices as power-up. Improperly powering down your AMD device can result in memory corruption, stalled I/O communications, and unexpected device behavior. The power-down sequence for the Versal device is the reverse of the power-on sequence unless stated otherwise in the PDM. When powering down each rail in sequence, the previous rail in the power-down sequence must reach 5% of its target value before the next rail in the sequence can begin to ramp down. It must be monotonic with no plateaus and each rail should power down within 0.2 ms to 40 ms. The POR_B signal is not required for the power-down sequence. If there are no power-down capabilities in the system, a simultaneous power down of all rails is acceptable as long as the system is not writing to memory or communicating via the I/Os.

Figure 1. Power-down Sequence Example

Output capacitance from the VRM and the PDN might impact a rails power-down timing. If there is a large amount of capacitance, it can take longer for the capacitance to drain its charge. A bleed resistor can be added to the output to reduce the capacitance discharge time. There are also voltage regulators that integrate bleed resistors by using internal field-effect transistors (FETs) within the IC that activate when the device is powered down.