FPGAs and adaptive SoCs have many supported rail consolidations to simplify power delivery and sequencing that fall into two main groups. The minimum rails grouping combines power rails of identical voltages to reduce the number of regulators required to power a device. Full-power management separates these rails into their respective domains to allow for a partial power down of the device to achieve greater power savings.
Different domains in Versal devices can be powered on in parallel. The following figure illustrates the recommended rail grouping for Versal AI Core devices with the highest flexibility of power rail management recommended for power-conscious applications that are battery powered, or to reduce overall power dissipation. The numbers listed beside each rail in the figure are the sequence order for power up and power down. The colors represent the domain they are associated with, and as mentioned, these can sequence in parallel following the sequence within each domain. Clock gating is also an option for power savings, but careful consideration must go into the transient step implications of using this method.
In the example in the figure, each domain is powered separately, and the power sequence is based by power domain. The numbers indicate the order for power on for that domain's sequence. An example of using this rail grouping to save power is powering down the gigabit transceivers when they are not in use. Another example is to power down an entire domain if entering a power saving mode.
Another popular rail consolidation is the minimum rails grouping that reduces the number of regulators required in the system by combining rails with identical voltages to reduce cost. However, this method limits the ability to power down domains not in use, as a single regulator might be powering more than one internal block of the Versal device. In this case, power management flexibility is sacrificed to reduce the number of regulators required, and means the PL, full-power domain (FPD), low-power domain (LPD), and PMC domain rails power together. Dynamic power savings are still possible via principles such as clock gating, frequency scaling, logic RST, or disabling power islands in the processing subsystem.
For AMD supported rail groupings/consolidations, the AMD power partners provide power delivery reference designs that have been confirmed to meet the specifications from AMD. Versal devices can experience differing slew rates that the voltage regulator is expected to respond to in the range from 10A/μs for a rail on the processing system and up to 200A/μs for VCCINT. See the Power Efficiency website for a list of power delivery reference designs with both validation in hardware and by design.