Power-up Sequencing

Simplified Power Sequencing (XAPP1375)

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1.1 English

Power-up sequencing is becoming more of a hard requirement for modern adaptive SoCs. The POR_B input must be asserted Low during the power-on sequence and continue to be asserted for a minimum duration of TPOR_B (10 μs) after all the required supplies of the active domains have reached their final voltages. Additional power management is required to power only the platform management controller (PMC) and then actively manage power to the processing system and programmable logic domains. If additional power management is not employed, all domain voltages must be at their final voltages at the release of POR_B. Before the deassertion of POR_B, the REF_CLK must be operating within specification. POR_B is not required for power-down sequencing.

The timings for the power-up sequence are shown in the following figure. The ramp time (TRAMP) is the time in which the VRM must ramp up the voltage to 95% of its final value within 0.2 ms to 40 ms. There is no defined time delay (TDELAY) specification between the power up of rails, but it is recommended to avoid long delays between rails as described in Answer Record 76259. Once the previous rail has reached its target voltage, the next rail in the sequence can begin its ramp up. AMD FPGAs and adaptive SoCs require that the voltages on all rails are ramped up monotonically, i.e., the voltage does not decrease after it has begun to ramp up.

Figure 1. Power-up Sequence Example
The sequencing controller can assume the time delays before the powering of the next rail. For example, if the regulator takes 10 ms to power up, a time delay of this value can be added before the next rail begins to power up. Alternatively, feedback can be implemented to the controller/sequencer from the regulators using the power good (PG) signals to determine that the rail has successfully powered on. This is the preferred method for safety applications for full visibility of a successful sequence but also adds complexity.