Revision History

Simplified Power Sequencing (XAPP1375)

Document ID
Release Date
1.1 English

The following table shows the revision history for this document.

Section Revision Summary
04/27/2023 Version 1.1
Summary Added SoC and FPGA information.
Power Sequencing: Definition and Purpose Renamed section from Features. Added references to additional power sequencing information. Add dynamic voltage scaling information.
Relative Sequencing Added information for a ratiometric ramp of two rails that share a power sequence slot.
Power-up Sequencing Added new section.
Power-down Sequencing Added additional power-down sequence details, as well as a figure illustrating a power-down sequence example.
Example Using Versal AI Core Full-power Management Grouping Reorganized this section. Added HBM, fuse, and battery to the Versal AI Core Full-power Management Rails Grouping figure and the AI Core Minimum Rails Grouping figure.
Method 4: FPGA Added note.
References Added reference to Power Design Manager User Guide (UG1556).
05/06/2022 Version 1.0
Initial release. N/A