Power Sequencing: Definition and Purpose

Simplified Power Sequencing (XAPP1375)

Document ID
XAPP1375
Release Date
2023-04-27
Revision
1.1 English

Briefly, power sequencing is the order in which voltage is applied to and disconnected from the power rails of a system. It is conducted in a controlled manner with defined time intervals between each rail for both power-up and power-down. Power sequencing is generally determined by the order in which the voltage regulator modules (VRMs) in a system are enabled/disabled or controlled via switches.

Power sequencing is a requirement for FPGAs and adaptive SoCs to reduce inrush currents, ensure correct and reliable operation, and maintain overall system health. It requires a set delay between the power supplies for power-up and power-down within specified ramp times. Improperly sequencing a device can result in inefficiencies, unknown I/O states, and potentially incorrect operation. In many cases, designers wait until the end of the design cycle to think about power sequencing, which can result in an ad hoc implementation. Regardless of the AMD device, power sequencing is an important part of the power design. The power sequencing methodology should be part of the design planning from the beginning to help create an optimal overall solution.

The latest power sequence for Versal devices is available in the power estimation tools available at Power Estimation. Versal devices that require dynamic voltage scaling (DVS) do not have any additional considerations for power sequencing and the recommended rail consolidation for -2LLI devices in the power design manager (PDM) should be followed.