Using Breakpoints - 2024.1 English

Vivado Design Suite Tutorial: Logic Simulation (UG937)

Document ID
UG937
Release Date
2024-06-12
Version
2024.1 English
A breakpoint is a user-determined stopping point in the source code used for debugging the design. When simulating a design with set breakpoints, simulation of the design stops at each breakpoint to verify the design behavior. After the simulation stops, an indicator shows in the text editor next to the line in the source file where the breakpoint is set, so you can compare the Wave window results with a particular event in the HDL source.

You use breakpoints to debug the error with the low frequency signal output that you previously observed. The erroneous sine[19:0] output is driven from the sineGen VHDL block. Start your debugging with this block.

  1. Select the U_SINEGEN scope in the Scope window to list the objects of that scope in the Objects window.
  2. In the Objects window, right-click sine[19:0] and use Go to Source Code to open the sinegen.vhd source file in the Text Editor.
    Tip: If you do not see the sine[19:0] signal in the Objects window, make sure that the filters at the top of the Objects window are set properly to include Output objects.

    Looking through the HDL code, the clk, reset, and sel inputs are correct as expected. Set your first breakpoint after the reset asserts low at line 137.

  3. Scroll to line 137 in the file.

    Add a breakpoint at line 137 in sinegen.vhd. Note that the breakpoint can be set only on the executable lines. The AMD Vivado™ simulator marks the executable lines with an empty red circle , on the left hand margin of the Text Editor, beside the line numbers.

    Setting a breakpoint causes the simulator to stop at that point, every time the simulator processes that code, or every time the counter is incremented by one.

  4. Click the red circle in the left margin, to set a breakpoint, as shown in the following figure.

    Observe that the empty circle becomes a red dot to indicate that a breakpoint is set on this line. Clicking on the red dot removes the breakpoint and reverts it to the empty circle .



    Note: To delete all breakpoints in the file, right-click on one of the breakpoints and select Delete All Breakpoints.

    Debugging in the Vivado simulator, with breakpoints and line stepping, works best when you can view the Tcl Console, the Waveform window, and the HDL source file at the same time, as shown in the following figure.

  5. Resize the windows, and use the window Float command or the New Vertical Group command to arrange the various windows so that you can see them all.
  6. Click the Restart button to restart the simulation from time 0.
  7. Run the simulation by clicking the Run All button .

    The simulation runs to time 102.5 ns, or near the start of first counting, and stops at the breakpoint at line 137. The focus within the Vivado IDE changes to the Text Editor, where it shows the breakpoint indicator and highlights the line.

    A message also displays in the Tcl Console to indicate that the simulator has stopped at a specific time, displayed in picoseconds, indicating the line of source code last executed by the simulator.



    Tip: When you have arranged windows to perform a specific task, such as simulation debug in this case, you can save the view layout to reuse it when needed. Use the Layout > Save Layout As command from the main menu to save view layouts. See the Vivado Design Suite User Guide: Using the Vivado IDE (UG893) for more information on arranging windows and using view layouts.
  8. Continue the simulation by clicking the Run All button .

    The simulation stops again at the breakpoint. Take a moment to examine the values in the Waveform window. Notice that the sine[19:0] signals in the Outputs group are uninitialized, as are the sine_l[15:0] signals in the Internal Signals group.

  9. In the Text Editor, add another breakpoint at line 144 of the sinegen.vhd source file.

    This line of code runs when the value of sel is 0. This code assigns the low-frequency signal, sine_l, with bit extension to the output, sine.

  10. In the Waveform window, select sine_l[15:0] in the Internal Signals group, and holding Ctrl, select sine[19:0] in the Outputs group.

    These selected signals are highlighted in the Waveform window, making them easier for you to monitor.

  11. Run the simulation by clicking the Run All button .

    Once again, the simulation stops at the breakpoint, this time at line 144.