Introduction - 2024.1 English

Vivado Design Suite Tutorial: Logic Simulation (UG937)

Document ID
UG937
Release Date
2024-06-12
Version
2024.1 English

This AMD Vivado™ Design Suite tutorial provides designers with an in-depth introduction to the Vivado simulator.

Video: You can also learn more about the Vivado simulator by viewing the quick take video at Vivado Logic Simulation.
Training: AMD provides training courses that can help you learn more about the concepts presented in this document. Use these links to explore related courses:

The Vivado simulator is a Hardware Description Language (HDL) simulator that lets you perform behavioral, functional, and timing simulations for VHDL, System Verilog, and mixed-language designs. The Vivado simulator environment includes the following key elements:

xvhdl and xvlog
Parsers for VHDL and Verilog/SV files, respectively, that store the parsed files into an HDL library on disk.
xelab
HDL elaborator and linker command. For a given top-level unit, xelab loads up all sub-design units, translates the design units into executable code, and links the generated executable code with the simulation kernel to create an executable simulation snapshot.
xsim
Vivado simulation command that loads a simulation snapshot to effect a batch mode simulation, or a GUI or Tcl-based interactive simulation environment.
Vivado Integrated Design Environment (IDE)
An interactive design-editing environment that provides the simulator user-interface.