Step 1: Preparing the Simulation - 2024.1 English

Vivado Design Suite Tutorial: Logic Simulation (UG937)

Document ID
Release Date
2024.1 English

The AMD Vivado™ simulator Non-Project Mode flow lets you simulate your design without setting up a project in the AMD Vivado™ IDE.

You can compile the HDL files in a design, and create a simulation snapshot by either:

  • Creating a Vivado simulator project script, specifying all HDL files to be compiled, and using the xelab command to create a simulation snapshot, or
  • Using specific Vivado simulator parser commands, xvlog and xvhdl, to parse individual source files and write the parsed files into an HDL library on disk, and then using xelab to create a simulation snapshot from the parsed files.