Creating a New Project - 2024.1 English

Vivado Design Suite Tutorial: Logic Simulation (UG937)

Document ID
UG937
Release Date
2024-06-12
Version
2024.1 English
  1. Create a new Vivado RTL project, targeting to the required device.
  2. Add the directories src and verif to the project by clicking on the + button. Both of these directories are in the Adder_4_bit directory.
  3. Mention the UVM verification files for simulation only.

  4. After the hierarchy is updated, ensure to select adder_4_bit_tb_top.sv file as top module.

  5. For UVM, you need to provide test name, here the test name is adder_4_bit_basic_test. For this add -testplusarg UVM_TESTNAME=adder_4_bit_basic_test -testplusarg UVM_VERBOSITY=UVM_LOW to xsim.more_options

  6. Launch simulation.

    This can run simulation for 1000 ns by default. Click run all to complete the simulation. You can see following in Tcl console.

Following are the steps to use UVM in Non-Project/Batch Mode:

  1. To run the simulation in non-project mode, change the current working directory to the run folder. cd ./Adder_4_bit/run
  2. For standalone simulation in Vivado you can source run_xsim.csh on Linux and run_xsim.bat on windows or source run.tcl using the below command in Linux/Windows. Vivado –mode batch –source run.tcl
  3. Once the simulation gets finished you can observe the UVM test results in the Shell or command prompt as shown in the following figure.

Directory Structure of both project and non project mode:

  • src & verif - Design and verification environment related files.
  • Run - Location to run simulation in Non project mode.
  • UVM_test - Project Mode XSIM simulation.