Concurrent Assertion - 2024.1 English

Vivado Design Suite Tutorial: Logic Simulation (UG937)

Document ID
UG937
Release Date
2024-06-12
Version
2024.1 English

This assertion is based on clock semantic and use sampled value of their expression. These assertions can expand over multiple cycle.

always@ (posedge clk)
    a1: assert property (a ##2 b);

a2: assert property (@(posedge clk) a ##2b);

In AMD Vivado™ simulator, the concurrent assertion of the second form that is used outside the procedural block is supported.

  1. In Tcl Console, invoke close_sim command to close the simulation running previously.
  2. In Tcl Console, invoke reset_simulation command to clean the simulation directory.
  3. In Tcl Console, invoke launch_simulation command to run the simulation.
  4. In Tcl Console, invoke the following command:
    current_scope /axi_vip_0__exdes_adv_mst_active_pt_mem__slv_passive/DUT/ex_design/axi_vip_passthrough/inst/IF/PC


  5. Double-click the scope PC to open the source code.
  6. Observe that line number 1144 onwards all the property declarations and assertions have been used.