Random Constraint - 2024.1 English

Vivado Design Suite Tutorial: Logic Simulation (UG937)

Document ID
UG937
Release Date
2024-06-12
Version
2024.1 English

System Verilog has a random constraint, which is used to generate a random value. Using this feature, you can even set the constraint on a random variable.

For each simulation, the simulator is supposed to generate a fixed set of values. In this example, randomize call is happening 10 times so each time the simulator is expected to assign a different value on variable ‘b1.' If we close the simulation and run it again, the simulator is expected to give the same 10 sets of values as the previous run. This is called random stability.

module top();
class c1;
rand bit [3:0] b1;
endclass
c1 obj1 = new();
initial
begin
    for(int i = 0; i < 10; i++)
    begin
        #5 obj1.randomize();
        $display("At time %t the value is %p", $time, obj1);
   end
end
endmodule

If you want different set of values, you should change the random seed value. In AMD Vivado™ simulator, it is done by passing -sv_seed option to xsim. In Tcl Console, you need to invoke the following command:

set_property -name {xsim.simulate.xsim.more_options} -value {-sv_seed 2000} -objects [get_filesets sim_adv_mst_active__pt_passive__slv_comb]

With seed, you have to provide any integer value. So just by changing a ‘seed’ value, you can get a different value. You do not need to do compilation and elaboration again.

  1. Add the following code in a file and name it as random.sv.
    module top();
    class c1;
    rand bit [3:0] b1;
    endclass
    c1 obj1 = new();
    initial
    begin
        for(int i = 0; i < 10; i++)
        begin
            #5 obj1.randomize();
            $display("At time %t the value is %p", $time, obj1);
       end
    end
    endmodule
  2. Perform the following:
    1. Invoke xvlog -sv random.sv command to compile the code.
    2. Invoke xelab top -s top command to elaborate the code.
    3. Invoke xsim top run -all command to simulate the code.
    Observe the output.

    run -all

    At time                 5000 the value is '{b1:3}
    At time                10000 the value is '{b1:7}
    At time                15000 the value is '{b1:7}
    At time                20000 the value is '{b1:0}
    At time                25000 the value is '{b1:0}
    At time                30000 the value is '{b1:5}
    At time                35000 the value is '{b1:9}
    At time                40000 the value is '{b1:3}
    At time                45000 the value is '{b1:12}
    At time                50000 the value is '{b1:0}
    
  3. Type in "exit" to leave the simulation and then re-run step 2c and notice the value is similar to the previous one.
    Note: If you are running this in the AMD Vivado™ GUI, exiting will exit all of Vivado and you will need to do all of step two again, not just 2c.
  4. Simulate the code with different SV seed xsim top -sv_seed 5000 and observe that the value is different. Thus, you can generate different values without going through compile and elaboration steps.