Overview - 2024.1 English

Vivado Design Suite Tutorial: Logic Simulation (UG937)

Document ID
UG937
Release Date
2024-06-12
Version
2024.1 English

PAM4 encodes 2-bits of binary data into four voltage levels. Through this tutorial, we can create an example to verify designs with PAM4 signals.

Since four voltage levels are not supported by implementation tools. So, the PAM4 connections are created as regular single-bit wires. For simulation purposes, the PAM4 signals of the design are made accessible in the testbench via integer ports of a special module (xil_dut_bypass) that gets generated as part of this flow. The generated bypass module is not part of the DUT but has direct access to the PAM4 signals of the DUT. This module can be instantiated in the testbench to directly drive/observe PAM4 signals.