Feature Covered - 2024.1 English

Vivado Design Suite Tutorial: Logic Simulation (UG937)

Document ID
UG937
Release Date
2024-06-12
Version
2024.1 English
The following features are covered in the GTM-Wizard:
  1. Detection of designs with PAM4 signals, designs instantiating GTM_DUAL and automatic generation bypass module (xil_dut_bypass).
  2. Simple sanity check for the design that should instantiate bypass module.
  3. A mechanism to view PAM4 signals in Waveform Viewer for XSim users.
  4. Provide a way to generate a bypass module for export simulation flow.

In this tutorial, we would generate a GTM-Wizard example design, which uses a PAM4 signal. To generate that, follow the steps below:

  1. Create a project in Vivado 2024.x without adding a source/constraint file Create project > next > next > next > next > next.
  2. In the Default Part page, select Virtex UltraScale+ 58G and select parts as shown in the following figure, and click Next.
  3. Check the summary report and click Finish.
  4. Under Project Manager, click on IP Catalog and search for gtm_wizard and then double-click Virtex UltraScale+ FPGAs Transceivers Wizard.
  5. Click OK on default configuration and click Skip on Generate Output Product dialog box.
  6. On Sources window, right-click the generated XCI file, click Open IP Example Design, and specify the location.

    At this stage, you have an example ready to run the simulation.

Before heading towards simulation, here are a few things from the PAM4 point of view:

  1. xil_dut_bypass module definition is generated on runtime by the tool that contains a hierarchical reference to GTM_DUAL.
  2. This xil_dut_bypass module generation is controlled by the Configure Design for Hierarchical Access option, which is set by default.
    Note: For old behavior, uncheck Configure Design for Hierarchical Access.

    Once the design is created, we can run it either through launch_simulation or export_simulation.

Launch_simulation
  1. Click Run Behavioral Simulation. This will run the simulation with Vivado Simulator.
  2. Once the snapshot is created and loaded, the simulation will stop after 1000 ns. Let us look at xil_dut_bypass definition. Double-click xil_dut_bypass in the Scope window to see the source file. Note the hierarchical reference from the top module to the leaf-level instance.
  3. Right-click xil_dut_bypass and add to waveform.