Step 7: Re-Simulating the Design - 2024.1 English

Vivado Design Suite Tutorial: Logic Simulation (UG937)

Document ID
UG937
Release Date
2024-06-12
Version
2024.1 English
With the various signals, signal groups, dividers, and attributes you have added to the Waveform window, you are now ready to simulate the design again.
  1. Click the Restart button to reset the circuit to its initial state.
  2. Click the Run All button .

    The simulation runs for about 7005 ns. If you do not restart the simulator prior to executing the Run All command, the simulator runs continuously until interrupted.

  3. After the simulation is complete, click the Zoom Fit button to see the whole simulation timeline in the Waveform window. Figure below shows the current simulation results.