Switching Tab - 2024.1 English

Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)

Document ID
UG907
Release Date
2024-05-30
Version
2024.1 English

In the Switching tab, review the design’s Simulation and Default Activity Settings. The clocks constrained in the design can also be viewed on this page as shown in the following figure.

Figure 1. Report Power Switching Settings
Reset switching activity before report power
This check-box if enabled, clears/resets all the switching activity applied before running report power.
Switching Activity for Resets
Sets the Switching Activity for control sets. See Deassertion of Resets for more information.
Simulation Settings
Simulation activity file (.saif)
AMD Vivado™ Report Power takes input SAIF simulation data generated for the design. Report Power then matches nets in the design database with names in the simulation results netlist. See Specifying Switching Activity for Power Analysis, for a description of how input from a simulation results (SAIF) file can be used for a more accurate power analysis.
Default Activity Settings
Default toggle rate
The default toggle rate to be used in power analysis on the primary inputs of the design. The default toggle rate is set on those primary input nets whose switching activity is not specified by the user, simulation data or constraints of the design. On asynchronous inputs the toggle rate is set with respect to the capturing clock in the design. Valid values are: 0 <= value < 100. The default value is 12.5.
Default Static Probability
The default static probability to be used in power analysis on the design. The default static probability is set on those primary inputs whose switching activity is not specified by the user, simulation data or constraints of the design. Valid values are: 0 <= value <= 1. The default value is 0.5.
Enable Rate Settings
Block RAM Port Enable
Sets the activity rate of all the Block RAM enable signals of the design to the value specified.
Block RAM Write Enable
Sets the activity rate of all the Block RAM write enable signals of the design to the value specified.
Bidi Output Port Enable
Sets the activity rate of all the Bidirectional I/O enable signals (T pin of IOBUF) of the design to the value specified.
Note: Specify Static Probability and the Toggle Rate together.
Toggle Rate Settings
Primary Outputs
Sets the switching activity rate of all the enable signals (i.e., T pin of OBUFT) of the primary outputs of the design to the value specified.
Logic
Registers
Sets switching activity rate on Output pins of all the Registers in the design.
Shift Registers
Sets switching activity rate on Output pins of all the Shift Registers in the design.
Distributed RAMs
Sets switching activity rate on Data Outputs pins of all the Distributed RAMs in the design.
LUTs
Sets switching activity rate on Outputs pins of all the LUTs in the design.
DSPs
Sets switching activity rate on Data Outputs pins of all the DSPs in the design.
Block RAMs
Sets switching activity rate on Data Outputs pins of all the Block RAMs in the design.
GTs (Serial Transceivers)
RX Data
Sets switching activity rate on RX Data Output pins of all the GTs in the design.
TX Data
Sets switching activity rate on TX Data Output pins of all the GTs in the design.
Note: Specify Static Probability and Toggle Rate together. See the description of the set_switching_activity command under Netlist Element Activity, for more information and guidelines.
Constrained Clocks
Expanding Constrained Clocks lists all the clocks that are constrained in the design. Review the clock frequencies and ensure they are accurate.
Tip: Make sure all primary clocks are specified. The design clocks are identified based only on create_clock or create_generated_clock constraints.