Experiment within RTL Code - 2023.2 English

Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)

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2023.2 English

If you need to modify your RTL code to reduce power you can experiment with adding a pipeline or performing power retiming around high-activity logic such as carry chains and XOR functions. Although long paths with carry chains tend to be on slower clock domains, they exhibit more glitching activity, which increases the design power. Retiming or pipelining these paths is often beneficial.