Block RAM Cascade Optimizations - 2024.1 English

Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)

Document ID
UG907
Release Date
2024-05-30
Version
2024.1 English

If block RAMs are found to be cascaded, because only one block RAM can be active at any time, the rest of the block RAMs can be disabled based on address and any existing enable conditions. This enables large power savings. These optimizations are performed by default in the opt_design phase in the AMD Vivado™ Design Suite.

Versal adaptive SoC block RAM Power Optimization only includes two types of optimizations:
Write Mode Optimization
Change the WRITE_MODE to NO_CHANGE if the output is not consumed on the following clock cycle.
Structural Optimization
Swap the EN and WE on write-only ports to reduce enable time.