Power Estimation Expectations - 2023.2 English

Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)

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2023.2 English

As your design flow progresses through synthesis and implementation you will want to monitor and verify the power consumption regularly. You must ensure that thermal dissipation remains within budget so that you can detect and act early on if any area approaches your constraints. The accuracy of the power estimates varies depending on the design stage when the power was estimated.

You can compare the estimated power from the Power Estimation to the power analysis results to validate assumptions made during estimation. If power analysis shows that the power is much higher than estimated, you need to revisit Power Estimation to evaluate the thermal design.

Importing an XDC Constraint (*.xdc) File

Use this format to export the XPE/PDM environmental, thermal and budget information in the form of Xilinx design constrains (*.xdc) file using the set_operating_condition commands. The exported file can be sourced in Vivado project to get the same design constraints as set in XPE/PDM. This file will have the following information in the exported *.xdc file:

  • Device Process
  • Junction Temperature
  • Ambient Temperature
  • Airflow
  • Heat sink
  • Board and board layers
  • Voltage
  • Design Power Budget
Note:  The PDM tool supports exporting power rails consolidation.