AI Engine-ML - 2024.1 English

Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)

Document ID
UG907
Release Date
2024-05-30
Version
2024.1 English

AI Engine-ML (AIE-ML) is available in Versal AI Edge series and a few Versal AI Core series devices. The compute tiles are similar to AI-Engine tiles with additional support for BFloat data type. AI-Engine-ML has additional shared memory tiles for improved performance and data movement.

The maximum total supported memory by memory tile is upto 38 MB across AIE Array, depending on the device. Memory Tile memory banks have 512 KB SRAM, arranged in 16 physical banks, each 128-bit wide and 2K words deep. Report_power can generate a .xpe file, which you can import in PDM. All the configuration parameters are passed on from Vitis design sources.

Figure 1. AI Engine-ML

For more information please to Versal Adaptive SoC AIE-ML Architecture Manual (AM020).