DSP - 2024.1 English

Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)

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2024.1 English

Unlike previous generation DSP blocks, the AMD Versalâ„¢ Adaptive SoC DSP block can be implemented as a complex multiplier and a floating-point adder and multiplier. It can implement a wide variety of arithmetic and logic functions like previous generation DSP blocks. DSP operations which are reported as DSP Mode in power report are listed here. For more information, see Versal Adaptive SoC DSP Engine Architecture Manual (AM004).

Legacy mode is compatible with the DSP48 from previous generations. INT24 indicates that the DSP block is configured as a 27x24 signed, fixed point multiplier.
DSP58 uses the Vector Fixed Point ALU mode in this configuration. This mode is used for computing three-element 9x8 vector dot products with accumulate or post add options.
This mode indicates that two adjacent DSP58 blocks are configured to implement an 18-bit complex multiplier.
In this mode, DSPFP32 primitive is used as a floating-point multiplier and adder. This mode is used for FP32 single precision or FP16 half precision with accumulate or post add options.
Note: It is recommended to re-target your existing designs to DSP58 for taking complete advantage of the architectural improvements in the DSP58 blocks.
Tip: DSP output toggle rate does not change much with the data input toggle rate. It mainly depends on specific DSP operations (Multiply-Only, Multiply-Add, and Multiply-Accumulate) and various DSP modes (INT24, INT8, CINT18, and FP32).

The following figure shows report_power results for DSP primitive:

Figure 1. DSP View