In XPE or PDM you can import the AMD Vivado™ power analysis results from modules developed by multiple sources to review the total power once these separate IP blocks are implemented in the device. You can also evaluate situations where you would have to change the netlist, and evaluate the power implications, without having to actually make the code changes. For your design core logic, XPE or PDM works at a coarser resolution than the Vivado power analysis, because you cannot adjust each logic element or signal individually in XPE or PDM. In XPE or PDM, you can also experiment with:
- Resource usage
- Explore reducing the resource count. Try remapping pieces of logic from slice logic to dedicated blocks such as block RAM or DSP, and vice versa.
- Resource configuration
- Explore using different configuration settings for the design I/Os, block RAMs, clock generators, and other resources.