Versal Adaptive SoC Boot Image Format - 2023.2 English

Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400)

Document ID
UG1400
Release Date
2023-12-13
Version
2023.2 English

The following is a diagram of the components that can be included in an AMD Versal™ adaptive SoC boot image called programmable device image (PDI).

Platform Management Controller

The platform management controller (PMC) in Versal adaptive SoC is responsible for platform management of the Versal adaptive SoC, including boot and configuration. This chapter is focused on the boot image format processed by the two PMC MicroBlaze processors, the ROM code unit (RCU), and the platform processing unit (PPU):

RCU
The ROM code unit contains a triple-redundant MicroBlaze processor and read-only memory (ROM) which contains the executable BootROM. The BootROM executable is metal-masked and unchangeable. The MicroBlaze processor in the RCU is responsible for validating and running the BootROM executable. The RCU is also responsible for post-boot security monitoring and physical unclonable function (PUF) management.
PPU
The platform processing unit contains a triple-redundant MicroBlaze processor and 384 KB of dedicated PPU RAM. The MicroBlaze in the PPU is responsible for running the platform loader and manager (PLM).
In Versal adaptive SoC, the adaptable engine (PL) consists of rCDO and rNPI files. The rCDO file mainly contains CFrame data along with PL and NoC power domain initialization commands. The rNPI file contains configuration data related to the NPI blocks. NPI blocks include NoC elements: NMU, NSU, NPS, NCRB; DDR, XPHY, XPIO, GTY, MMCMs, and so on.
Note: AMD Versal™ adaptive SoC includes SSI technology devices. For more information, see SSIT Support.
Figure 1. Versal Adaptive SoC Boot Image Block Diagram

Figure 2. Versal Adaptive SoC Boot Image Block Diagram Part II