Getting Started with Vitis
Navigating Content by Design Process
Vitis Software Platform Release Notes
What's New
Embedded GNU Toolchain Details
Changed Behavior
Known Issues
Unified IDE Features versus Classic IDE Features
Installation
Installation Requirements
Installer Types
Requirements and Setup
Supported Operating System
Operating Systems End-of-Life Notification
Required Libraries
Download the Installation File
Vitis Software Platform Installation
Installing the Vitis Software Platform
Lightweight Installer Download
Prepare to Install the Tool
Run the Installation File
Setting Up the Environment to Run the Vitis Software Platform
Getting Started with the Vitis Software Platform
Vitis Unified Software Platform Overview
Vitis Software Development Workflow
Workspace Structure in the Vitis Software Platform
Migrating from the Classic Vitis IDE to Vitis Unified IDE
Standalone Application Component Migration Details
Using the Vitis Unified IDE
Launching the Vitis Unified IDE
Vitis Unified IDE Launch Options
Vitis Unified IDE View and Feature
Vitis Component View
Search View
Source Control
Debug View
Example View
Code View and Smart Editor
Preferences
Settings
Keyboard Shortcuts, Command Palette, and Quick Find
Parallel Compiling
Notification for File Change
New Feature Preview
Develop
Managing Platforms and Platform Repositories
Target Platform
Creating a Hardware Design (XSA File)
Creating a Platform Component from XSA
Customizing a Pre-Built Platform
Adding a Domain to an Existing Platform
Configuring a Domain
Domain Overview Page
Board Support Package Settings Page
Switching FSBL Targeting Processor
Modifying Source Code for FSBL
Modifying the Domain Sources (Driver and Library Code)
Creating a Software Repository
Adding the Software Repository
Resetting BSP Sources for a Domain
Updating the Hardware Specification
Reading Hardware Specification
Applications
Creating application component
Creating an Application Component from Examples
Creating an Application Component
Creating a System Project Component
Managing Multiple Applications in a System Project Component
Building Projects
Build Configuration Settings
Adding Symbols or Definitions
Adding Libraries and Library Paths
Specifying the Linker Options
Specifying Debug and Optimization Compiler Flags
Specifying Miscellaneous Compiler Flags
Linker Scripts
Generating a Linker Script for an Application
Manually Adding the Linker Script
Modifying a Linker Script
Building the Application Component
Reading ELF Disassembly
Changing a Referenced Domain
Creating a Library Project
Creating a User Application Template
Using Custom Libraries in Application Projects
Run, Debug, and Optimize
Launch Configurations
Main Page
Application Part
Target Connections
Creating a New Target Connection
Setting Custom JTAG Frequency
Establishing a Target Connection
Running the Application Component
Debugging Application Component
Starting Debug
Debugging Standalone Application Component
Debugging Linux Application Component
Debugging Standalone Application Component on QEMU
Setting Conditional Breakpoints
Viewing Disassembly Code
Viewing Memory
Viewing the Value of a Certain Memory address
Comparing the Memory Value of Two Addresses
Freezing Memory Value
Viewing Registers
Exporting Registers from the Vitis IDE
Debugging an Application Component Already Running On a Target Device
Set Up Path Mapping
Debugging an Application on the Emulator (QEMU)
Running and Debugging Application Components under a System Project Together
Debugging on a Remote Board
OS Aware Debugging
Xen Aware Debugging
Debugging Self-Relocating Programs
Debugging an Application Project Using the Emulator (Command-Line Flow)
Cross-Triggering
Enable Cross-Triggering
Cross-Triggering in Zynq Devices
Cross-Triggering in Zynq UltraScale+ MPSoCs
Cross-Triggering in Versal Devices
Use Cases
FPGA to CPU Triggering
PTM to CPU Triggering
CPU to CPU Triggering
XSCT Cross-Triggering Commands
Profile/Analyze
TCF Profiling
gprof Profiling
Non-Intrusive Profiling for MicroBlaze Processors
FreeRTOS Analysis using STM
Optimize: Performance Analysis
Creating a Boot Image
Programming Flash
Multi-Cable and Multi-Device Support
Viewing Target Connections
User Managed Flow
Setting User Specified Tool Chain
Vitis Utilities
Software Command-Line Tool
Program Device
Vitis Terminal
Project Export and Import
Generating Device Tree
Bootgen Tool
Introduction
Installing Bootgen
Boot Time Security
Boot Image Layout
Zynq 7000 SoC Boot and Configuration
Zynq 7000 SoC Boot Image Layout
Zynq 7000 SoC Boot Header
Zynq 7000 SoC Register Initialization Table
Zynq 7000 SoC Image Header Table
Zynq 7000 SoC Image Header
Zynq 7000 SoC Partition Header
Zynq 7000 SoC Partition Attribute Bits
Zynq 7000 SoC Authentication Certificate
Zynq 7000 SoC Authentication Certificate Header
Zynq 7000 SoC Boot Image Block Diagram
Zynq UltraScale+ MPSoC Boot and Configuration
Zynq UltraScale+ MPSoC Boot Image
Zynq UltraScale+ MPSoC Boot Header
Zynq UltraScale+ MPSoC Boot Header Attribute Bits
Zynq UltraScale+ MPSoC Register Initialization Table
Zynq UltraScale+ MPSoC PUF Helper Data
Zynq UltraScale+ MPSoC Image Header Table
Zynq UltraScale+ MPSoC Image Header
Zynq UltraScale+ MPSoC Partition Header
Zynq UltraScale+ MPSoC Partition Attribute Bits
Zynq UltraScale+ MPSoC Authentication Certificates
Zynq UltraScale+ MPSoC Authentication Certification Header
Zynq UltraScale+ MPSoC Secure Header
Zynq UltraScale+ MPSoC Boot Image Block Diagram
Versal Adaptive SoC Boot Image Format
Versal Adaptive SoC Boot Header
Versal Adaptive SoC Boot Header Attributes
Versal Adaptive SoC Image Header Table
Versal Adaptive SoC Image Header
Versal Adaptive SoC Partition Header
Versal Adaptive SoC Authentication Certificates
Versal Adaptive SoC Authentication Certification Header
Creating Boot Images
Boot Image Format (BIF)
BIF Syntax and Supported File Types
BIF Syntax for Versal Adaptive SoC
Attributes
Using Bootgen GUI
Launch Bootgen GUI
Bootgen GUI for Zynq 7000 and Zynq UltraScale+ Devices
Using Bootgen GUI Options for Versal Adaptive SoCs
Using Bootgen on the Command Line
Commands and Descriptions
Boot Time Security
Using Encryption
Encryption Process
Decryption Process
Encrypting Zynq 7000 Device Partitions
Encrypting Zynq MPSoC Device Partitions
Operational Key
Rolling Keys
Gray/Obfuscated Keys
Key Generation
Black/PUF Keys
Multiple Encryption Key Files
Encrypting Versal Device Partitions
Rolling Keys
Key Generation
Black/PUF Keys
Meta Header Encryption
Using Authentication
Signing
Verifying
Zynq UltraScale+ MPSoC Authentication Support
NIST SHA-3 Support
Bitstream Authentication Using External Memory
User eFUSE Support with Enhanced RSA Key Revocation
Key Generation
PPK Hash for eFUSE
Versal Authentication Support
Versal Hashing Scheme
Using HSM Mode
Creating a Boot Image Using HSM Mode: PSK is not Shared
Creating a Zynq 7000 SoC Device Boot Image using HSM Mode
Creating a Zynq UltraScale+ MPSoC Device Boot Image using HSM Mode
Creating a Versal Device Boot Image Using HSM
Generating the PDI
HSM Mode Steps
SSIT Support
FPGA Support
Encryption and Authentication
HSM Mode
HSM Flow with Both Authentication and Encryption
Use Cases and Examples
Zynq MPSoC Use Cases
Simple Application Boot on Different Cores
PMU Firmware Load by BootROM
PMU Firmware Load by FSBL
Booting Linux
Encryption Flow: BBRAM Red Key
Encryption Flow: Red Key Stored in eFUSE
Encryption Flow: Black Key Stored in eFUSE
Encryption Flow: Black Key Stored in Boot Header
Encryption Flow: Gray Key Stored in eFUSE
Encryption Flow: Gray Key Stored in Boot Header
Operational Key
Using Op Key to Protect the Device Key in a Development Environment
Single Partition Image
Authentication Flow
BIF File with SHA-3 eFUSE RSA Authentication and PPK0
XIP
Split with "Offset" Attribute
Versal Adaptive SoC Use Cases
Bootloader, PMC_CDO
Bootloader, PMC_CDO with Load Address
Enable Checksum for Bootloader
Bootloader, PMC_CDO, PL CDO, NPI
Bootloader, PMC_CDO, PL CDO, NPI, PS CDO, and PS ELFs
AI Engine Configuration and AI Engine Partitions
Appending New Partitions to Existing PDI
RSA Authentication Example
ECDSA Authentication Example
AES Encryption Example
AES Encryption with Key Rolling Example
AES Encryption with Multiple Key Sources Example
AES Encryption and Authentication Example
Replacing PLM from an Existing PDI
Replace PLM and PMC CDO in SSI technology PDIs
BIF Attribute Reference
aarch32_mode
aeskeyfile
alignment
auth_params
authentication
big_endian
bbram_kek_iv
bh_kek_iv
bh_keyfile
bh_key_iv
bhsignature
blocks
boot_config
boot_device
bootimage
bootloader
bootvectors
checksum
copy
core
delay_auth
delay_handoff
delay_load
destination_cpu
destination_device
early_handoff
efuse_kek_iv
efuse_user_kek0_iv
efuse_user_kek1_iv
encryption
exception_level
familykey
file
fsbl_config
headersignature
hivec
id
image
imagestore
init
keysrc
keysrc_encryption
load
metaheader
name
offset
optionaldata
overlay_cdo
parent_id
partition
partition_owner, owner
pid
pmufw_image
ppkfile
presign
pskfile
puf_file
reserve
split
spkfile
spksignature
spk_select
sskfile
startup
trustzone
type
udf_bh
udf_data
userkeys
xip_mode
Command Reference
arch
authenticatedjtag
bif_help
dual_ospi_mode
dual_qspi_mode
dump
dump_dir
efuseppkbits
enable_auth_opt
encrypt
encryption_dump
fill
generate_hashes
generate_keys
h, help
image
log
nonbooting
o
p
padimageheader
process_bitstream
read
spksignature
split
verify
verify_kdf
w
zynqmpes1
Initialization Pairs and INT File Attribute
CDO Utility
Accessing
Usage
Command Line Options
Address Filter File
Examples
Converting Binary to Source without Annotations
Converting Binary to Source with Annotations
Editing Binary CDO File
Converting Source to Binary
Design Advisories for Bootgen
Vitis Python CLI
Python Vitis Commands
Python API: A command-line tool for creating and managing projects in Vitis
Managing Vitis IDE Components through Python APIs
System Project
Script Building Logger: Tool to Automate Script Creation Based on IDE Actions
Python XSDB Commands
Python XSDB Usage Examples
Software Command-Line Tool
Software Command-Line Tool
XSCT Commands
Target Connection Management
connect
disconnect
targets
gdbremote connect
gdbremote disconnect
Target Registers
rrd
rwr
Program Execution
state
stop
con
stp
nxt
stpi
nxti
stpout
dis
print
locals
backtrace
bt
profile
mbprofile
mbtrace
Target Memory
mrd
mwr
osa
memmap
Target Download FPGA/BINARY
dow
verify
fpga
Target Reset
rst
IPI commands to Versal PMC
plm
plm copy-debug-log
plm set-debug-log
plm set-log-level
plm log
Target Breakpoints/Watchpoints
bpadd
bpremove
bpenable
bpdisable
bplist
bpstatus
Jtag UART
jtagterminal
readjtaguart
Miscellaneous
loadhw
loadipxact
unloadhw
mdm_drwr
mb_drwr
mdm_drrd
mb_drrd
configparams
version
xsdbserver start
xsdbserver stop
xsdbserver disconnect
xsdbserver version
JTAG Access
jtag targets
jtag sequence
jtag device_properties
jtag lock
jtag unlock
jtag claim
jtag disclaim
jtag frequency
jtag skew
jtag servers
Target File System
tfile open
tfile close
tfile read
tfile write
tfile stat
tfile lstat
tfile fstat
tfile setstat
tfile fsetstat
tfile remove
tfile rmdir
tfile mkdir
tfile realpath
tfile rename
tfile readlink
tfile symlink
tfile opendir
tfile readdir
tfile copy
tfile user
tfile roots
tfile ls
SVF Operations
svf config
svf generate
svf mwr
svf dow
svf stop
svf con
svf delay
svf rst
Device Configuration System
device program
device status
device authjtag
STAPL Operations
stapl config
stapl start
stapl stop
Vitis Projects
openhw
closehw
getaddrmap
getperipherals
getprocessors
repo
lscript
lscript memory
lscript section
lscript def-mem
lscript generate
platform
platform active
platform clean
platform config
platform create
platform generate
platform list
platform report
platform read
platform remove
platform write
domain
domain active
domain config
domain create
domain list
domain remove
domain report
bsp
bsp config
bsp getdrivers
bsp getlibs
bsp getos
bsp listparams
bsp regenerate
bsp removelib
bsp setdriver
bsp setlib
bsp setosversion
library
library build
library clean
library create
library list
library remove
library report
checkvalidrmxsa
isstaticxsa
ishwexpandable
createdts
setws
getws
app
app build
app clean
app config
app create
app list
app remove
app report
app switch
sysproj
sysproj build
sysproj clean
sysproj list
sysproj remove
sysproj report
importprojects
importsources
toolchain
XSCT Use Cases
Common Use Cases
Changing Compiler Options of an Application Project
Creating an Application Project Using an Application Template (Zynq UltraScale+ MPSoC FSBL)
Creating an FSBL Application Project Using Manually Created Domain (Zynq UltraScale+ MPSoC FSBL)
Creating a Bootable Image and Program the Flash
Debugging a Program Already Running on the Target
Debugging Applications on Zynq UltraScale+ MPSoC
Selecting Target Based on Target Properties
Memory and Register accesses from XSCT
Memory accesses
Processor targets
Non-processor targets
The Effect of XPPU/XMPU on Memory Accesses
Register Accesses
Modifying BSP Settings
Performing Standalone Application Debug
Generating SVF Files
Program U-BOOT over JTAG
Running an Application in Non-Interactive Mode
Running Tcl Scripts
Switching Between XSCT and Vitis Integrated Design Environment
Using JTAG UART
Working with Libraries
Editing FSBL/PMUFW Source File
Editing FSBL/PMUFW Settings
Exchanging Files between Host Machine and Linux Running on QEMU
Loading U-Boot over JTAG
Hardware Software Interface (HSI) Commands
XSCT Interface Examples
HSI Tcl Examples
Accessing Hardware Design Data
Creating Standalone Software Design and Accessing Software Information
Generating and Compiling Applications with Customized Compiler Settings and Memory Sections
Generating and Compiling BSP with Advanced Driver/Library/OS/Processor Configuration
Generating and Compiling BSP for a Multi-Block Design
HSI Input and Output Files and Specifications
Input Files
XSA
Software Repository
Output Files
Generating Libraries and Drivers
MDD, MLD, and Tcl
MSS Parameters
Drivers
Libraries
OS Block
Microprocessor Software Specification (MSS)
MSS Overview
MSS Format
Global Parameters
Instance-Specific Parameters
OS, Driver, Library, and Processor Block Parameters
MLD/MDD Specific Parameters
OS-Specific Parameters
Processor-Specific Parameters
Microprocessor Library Definition (MLD)
Microprocessor Library Definition Overview
MLD Library Definition Files
MLD Format Specification
Tcl File Format Specification
MLD Parameter Descriptions
MLD Parameter Description Section
MLD Keywords
MLD Design Rule Check Section
MLD Tool Generation (Generate) Section
Microprocessor Driver Definition (MDD)
Microprocessor Driver Definition Overview
MDD Driver Definition Files
MDD Format Specification
MDD Format Examples
MDD Parameter Description
MDD Keywords
MDD Design Rule Check (DRC) Section
MDD Driver Generation (Generate) Section
Custom Driver
Microprocessor Application Definition (MAD)
Microprocessor Application Definition Overview
Microprocessor Application Definition Files
MAD Format Specification
MAD Format Example
HSI Commands
common::get_property
common::report_property
hsi::close_hw_design
hsi::create_dt_node
hsi::create_dt_tree
hsi::get_cells
hsi::get_dt_nodes
hsi::get_dt_trees
hsi::get_intf_nets
hsi::get_intf_pins
hsi::get_intf_ports
hsi::get_mem_ranges
hsi::get_nets
hsi::get_nodes
hsi::get_pins
hsi::get_ports
hsi::open_hw_design
GNU Compiler Tools
Overview
Compiler Framework
Common Compiler Usage and Options
Usage
Input Files
Output Files
File Types and Extensions
Libraries
Language Dialect
Commonly Used Compiler Options: Quick Reference
General Options
Library Search Options
Header File Search Option
Default Search Paths
Library Search Procedures
Header File Search Procedures
Initialization File Search Procedures
Linker Options
Memory Layout
Reserved Memory
I/O Memory
User and Program Memory
Object-File Sections
Linker Scripts
MicroBlaze Compiler Usage and Options
MicroBlaze Compiler
Processor Feature Selection Options
General Program Options
Application Execution Modes
Position Independent Code
MicroBlaze Application Binary Interface
MicroBlaze Assembler
MicroBlaze Linker Options
MicroBlaze Linker Script Sections
Tips for Writing or Customizing Linker Scripts
Startup Files
First Stage Initialization Files
Second Stage Initialization Files
Other Files
Modifying Startup Files
Reducing the Startup Code Size for C Programs
Compiler Libraries
Thread Safety
Command Line Arguments
Interrupt Handlers
Arm Compiler Usage and Options
Usage
Other Notes
C++ Code Size
C++ Standard Library
Position Independent Code (Relocatable Code)
Other Switches and Features
Embedded Design Tutorials
Drivers and Libraries
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
Revision History
Please Read: Important Legal Notices
crt0.o
This initialization file is used for programs which are to be executed in
standalone mode, without the use of any bootloader or debugging stub. This CRT
populates the reset, interrupt, exception, and hardware exception vectors and
invokes the second stage startup routine _crtinit
. On returning
from _crtinit
, it ends the program by infinitely looping in the
_exit
label.
crt1.o
This initialization file is used when the application is debugged in a
software-intrusive manner. It populates all the vectors except the breakpoint
and reset vectors and transfers control to the second-stage
_crtinit
startup routine.
crt2.o
This initialization file is used when the executable is loaded using a
bootloader. It populates all the vectors except the reset vector and transfers
control to the second-stage _crtinit
startup routine. On
returning from _crtinit
, it ends the program by infinitely
looping at the _exit
label. Because the reset vector is not
populated, on a processor reset, control is transferred to the bootloader, which
can reload and restart the program.
crt3.o
This initialization file is employed when the executable does not use any
vectors and wishes to reduce code size. It populates only the reset vector and
transfers control to the second stage _crtinit
startup routine.
On returning from _crtinit
, it ends the program by infinitely
looping at the _exit
label. Because the other vectors are not
populated, the GNU linking mechanism does not pull in any of the interrupt and
exception handling related routines, thus saving code space.