Debug Operations on Session Object
In this mode, you can create a session object and run debug operations on different debug targets using the same session object.
session=start_debug_session()
session.connect(url="TCP:xhdbfarmrkd11:3121")
session.targets(3)
# All subsequent commands are run on target 3, until the target is changed with targets() function
session.dow("test.elf")
session.bpadd(addr='main')
session.con()
session.targets(4)
# All subsequent commands are run on target 4
session.dow("foo.elf")
session.bpadd(addr='foo')
session.con()
Debug Operations on Target Object
You can also use the Target object returned by targets() functions and run debug operations can be performed on these objects. The following is an example:
session = start_debug_session()
session.connect(url="TCP:xhdbfarmrkd11:3121")
ta3 = session.targets(3)
ta4 = session.targets(4)
# Run debug commands using target objects
ta3.dow("test.elf")
ta4.dow("foo.elf")
bp1 = ta3.bpadd(addr='main')
bp2 = ta4.bpadd(addr='foo')
ta3.con()
ta4.con()
...
bp1.status()
bp2.status()
For interactive usage, it is recommended to use commands and options instead of functions and arguments, as functions require a lot of extra typing. You have defined an interactive() function in xsdb module, which supports the commands. The following is an example:
Vitis-ng [1]: import xsdb
Vitis-ng [2]: xsdb.interactive()
% conn -host xhdbfarmrkb9
tcfchan#0
% ta
1 APU
2 ARM Cortex-A9 MPCore #0 (Running)
3 ARM Cortex-A9 MPCore #1 (Running)
4 xc7z020
% ta 2
<xsdpy._target.Target object at 0x7fb2652d3520>
% stop
Info: ARM Cortex-A9 MPCore #0 (target 2) Stopped at 0xffffff28 (Suspended)
% q
Vitis-ng [3]:Programming U-Boot over JTAG
s = xsdb.start_debug_session()
# connecting to the target
s.connect(url="TCP:xhdbfarmrkg7:3121")
# Disable Security gates to view PMU MB target
s.targets("--set", filter="name =~ PSU")
# By default, JTAG security gates are enabled
# This disables security gates for DAP, PLTAP and PMU.
s.mwr(0xffca0038, words=0x1ff)
time.sleep(0.5)
# Load and run PMU FW
s.targets("--set", filter="name =~ MicroBlaze PMU")
s.dow('pmufw.elf')
s.con()
time.sleep(0.5)
# Reset A53, load and run FSBL
s.targets("--set", filter="name =~ Cortex-A53 #0")
s.targets()
s.rst(type='processor')
s.dow('fsbl.elf')
s.con()
# Give FSBL time to run
time.sleep(5)
s.stop()
# Downloading the other Softwares like u-boot..etc using below command
s.dow('system.dtb', '-d', addr=0x100000)
s.dow('u-boot.elf')
s.dow('bl31.elf')
s.con()
time.sleep(5)
s.stop()Generate SVF files
# Reset values of respective cores
core = 0
apu_reset_a53 = [0x380e, 0x340d, 0x2c0b, 0x1c07]
# Generate SVF file for linking DAP to the JTAG chain
# Next 2 steps are required only for Rev2.0 silicon and above.
s = xsdb.start_debug_session()
s.connect(url="TCP:xhdxxxx41x:3121")
svf = s.svf()
svf.config('--linkdap', scan_chain=[0x14738093, 12, 0x5ba00477, 4],
device_index=1, out="dapcon.svf")
svf.generate()
svf = s.svf()
# Configure the SVF generation
svf.config(scan_chain=[0x14738093, 12, 0x5ba00477, 4],
device_index=1, cpu_index=core, delay=10, out="fsbl_hello.svf")
# Record writing of bootloop and release of A53 core from reset
svf.mwr(0xffff0000, 0x14000000)
svf.mwr(0xfd1a0104, apu_reset_a53[core])
# Record stopping the core
svf.stop()
# Record downloading FSBL
svf.dow(file='zynq_fsbl.elf')
# Record executing FSBL
svf.con()
svf.delay(100000)
# Record some delay and then stopping the core
svf.stop()
# Record downloading the application
svf.dow(file='zynq_hello.elf')
# Record executing application
svf.con()
# Generate SVF
svf.generate()Using readjtaguart function
s = xsdb.start_debug_session()
# connecting to the target
s.connect(url="TCP:xhdbfarmrke9:3121")
# List available targets and select a target through its id.
# The targets are assigned IDs as they are discovered on the Jtag chain,
# so the IDs can change from session to session.
# For non-interactive usage, -filter option can be used to select a target,
# instead of selecting the target through its ID
s.targets("--set", filter="name =~ ARM Cortex-A9 MPCore #0")
s.targets()
s.rst()
s.loadhw(hw='zc702.xsa')
# run FSBL for ps7_init
s.dow('fsbl.elf')
s.con()
time.sleep(0.5)
s.stop()
# Download the application program
s.dow('test_jtag_uart.elf')
s.readjtaguart()
s.con()
s.readjtaguart('--stop') # after you are doneUsing readjtaguart_file function
s = xsdb.start_debug_session()
# connecting to the target
s.connect(url="TCP:xhdbfarmrke9:3121")
# List available targets and select a target through its id.
# The targets are assigned IDs as they are discovered on the Jtag chain,
# so the IDs can change from session to session.
# For non-interactive usage, -filter option can be used to select a target,
# instead of selecting the target through its ID
s.targets("--set", filter="name =~ ARM Cortex-A9 MPCore #0")
s.targets()
s.rst()
s.loadhw(hw='zc702.xsa')
# run FSBL for ps7_init
s.dow('fsbl.elf')
s.con()
time.sleep(0.5)
s.stop()
# Download the application program
s.dow('test_jtag_uart.elf')
s.readjtaguart(file='streams.log', mode='w')
s.con()
s.readjtaguart('--stop') # after you are doneUsing jtag_terminal function
s = xsdb.start_debug_session()
# connecting to the target
s.connect(url="TCP:xhdbfarmrke9:3121")
# List available targets and select a target through its id.
# The targets are assigned IDs as they are discovered on the Jtag chain,
# so the IDs can change from session to session.
# For non-interactive usage, -filter option can be used to select a target,
# instead of selecting the target through its ID
s.targets("--set", filter="name =~ ARM Cortex-A9 MPCore #0")
s.targets()
s.rst()
s.loadhw(hw='zc702.xsa')
# run FSBL for ps7_init
s.dow('fsbl.elf')
s.con()
time.sleep(0.5)
s.stop()
# Download the application program
s.dow('test_jtag_uart.elf')
s.jtagterminal()
s.con()
s.jtagterminal('--stop') # after you are donePerforming_standalone_app_debug:
Vitis [2]: import xsdb
Vitis [3]: s = xsdb.start_debug_session()
# connecting to the target
Vitis [4]: s.connect(url="TCP:xhdbfarmrke9:3121")
tcfchan#0
Out[4]: 'tcfchan#0'
# List available targets and select a target through its id.
# The targets are assigned IDs as they are discovered on the Jtag chain,
# so the IDs can change from session to session.
# For non-interactive usage, -filter option can be used to select a target,
# instead of selecting the target through its ID
Vitis [5]: s.targets()
1 APU
2 ARM Cortex-A9 MPCore #0 (Running)
3 ARM Cortex-A9 MPCore #1 (Running)
4 xc7z020
Vitis [6]: s.targets("--set", filter="name =~ APU")
Out[6]: <xsdb._target.Target at 0x7f01764c6e20>
Vitis [7]: s.targets()
1* APU
2 ARM Cortex-A9 MPCore #0 (Running)
3 ARM Cortex-A9 MPCore #1 (Running)
4 xc7z020
Vitis [8]: s.rst()
Vitis [9]: s.fpga(file='zc702.bit')
100% 3.86MB 1.66MB/s 00:02ETA
Vitis [10]: s.targets(2)
Out[10]: <xsdb._target.Target at 0x7f014d1f1610>
Vitis [11]: s.loadhw(hw='zc702.xsa')
INFO: [Hsi 55-2053] elapsed time for repository (/proj/xbuilds/HEAD_daily_latest/installs/lin64/Vitis/HEAD/data/embeddedsw) loading 1 seconds
# run FSBL for ps_init
Vitis [12]: s.dow('fsbl.elf')
Info: ARM Cortex-A9 MPCore #0 (target 2) Stopped at 0xffffff28 (Suspended)
Downloading Program -- fsbl.elf
section, .text: 0x00000000 - 0x0000fc8b
section, .handoff: 0x0000fc8c - 0x0000fcd7
section, .init: 0x0000fcd8 - 0x0000fce3
section, .fini: 0x0000fce4 - 0x0000fcef
section, .rodata: 0x0000fcf0 - 0x00010043
section, .data: 0x00010048 - 0x00013017
section, .mmu_tbl: 0x00014000 - 0x00017fff
section, .init_array: 0x00018000 - 0x00018003
section, .fini_array: 0x00018004 - 0x00018007
section, .rsa_ac: 0x00018008 - 0x0001903f
section, .bss: 0x00019040 - 0x0001b3ff
section, .heap: 0x0001b400 - 0x0001d3ff
section, .stack: 0xffff0000 - 0xffffd3ff
Successfully downloaded fsbl.elf
Setting PC to Program Start Address 0x00000000
Vitis [13]: s.con()
Info: ARM Cortex-A9 MPCore #0 (target 2) Running
Vitis [14]: s.stop()
Info: ARM Cortex-A9 MPCore #0 (target 2) Stopped at 0xfcac (Suspended)
# Download the application program
Vitis [15]: s.dow('test_jtag_uart.elf')
Downloading Program -- test_jtag_uart.elf
section, .text: 0x00100000 - 0x00101503
section, .init: 0x00101504 - 0x0010150f
section, .fini: 0x00101510 - 0x0010151b
section, .rodata: 0x0010151c - 0x001016cc
section, .data: 0x001016d0 - 0x00101b3f
section, .eh_frame: 0x00101b40 - 0x00101b43
section, .mmu_tbl: 0x00104000 - 0x00107fff
section, .init_array: 0x00108000 - 0x00108003
section, .fini_array: 0x00108004 - 0x00108007
section, .bss: 0x00108008 - 0x0010802f
section, .heap: 0x00108030 - 0x0010a02f
section, .stack: 0x0010a030 - 0x0010d82f
Successfully downloaded test_jtag_uart.elf
Setting PC to Program Start Address 0x00100000
Vitis [16]: s.bpadd(addr='main')
Out[16]: <xsdb._breakpoint.Breakpoint at 0x7f016fe59af0>
Info: Breakpoint 0 status:
target 2: {Address: 0x100564 Type: Hardware}
Info: Breakpoint 0 status:
target 3: {At col 4: Undefined identifier main. Invalid expression}
Vitis [17]: s.con()
Info: ARM Cortex-A9 MPCore #0 (target 2) Running
Info: ARM Cortex-A9 MPCore #0 (target 2) Stopped at 0x100570 (Breakpoint)
main() at ../src/helloworld.c: 57
57: int l_int_b = 20;
Vitis [18]: s.stp()
Info: ARM Cortex-A9 MPCore #0 (target 2) Running
Info: ARM Cortex-A9 MPCore #0 (target 2) Stopped at 0x100578 (Step)
main() at ../src/helloworld.c: 58
58: int l_int_a = 40;
Vitis [19]: s.stp()
Info: ARM Cortex-A9 MPCore #0 (target 2) Running
Info: ARM Cortex-A9 MPCore #0 (target 2) Stopped at 0x100580 (Step)
main() at ../src/helloworld.c: 60
60: init_platform();
Vitis [20]: s.rrd()
r0: 00000000 r1: 00000000 r2: 00000001
r3: 00000028 r4: 00000003 r5: 0000001e
r6: 0000ffff r7: f8f00000 r8: 0000767b
r9: ffffffff r10: 00000000 r11: 0010c02c
r12: 00000000 sp: 0010c020 lr: 001007bc
pc: 00100580 cpsr: 6000005f usr
fiq irq abt
und svc mon
vfp cp15 Jazelle
gpv_qos301_cpu gpv_qos301_dmac gpv_qos301_iou
gpv_trustzone l2cache mpcore
Vitis [21]: s.mrd(0xe000d000)
E000D000 : 800A0000
# Local variable value can be modified
Vitis [22]: s.locals()
l_int_b : 20
l_int_a : 40
Vitis [23]: s.locals(name='l_int_b', val=815)
Vitis [24]: s.locals(name='l_int_b')
l_int_b : 815
# Global variables and be displayed, and its value can be modified
Vitis [25]: s.print(expr='g_int_a')
g_int_a : 60
Vitis [26]: s.print(expr='g_int_a', val=9919)
Vitis [27]: s.print(expr='g_int_a')
g_int_a : 9919
# Expressions can be evaluated and its value can be displayed
Vitis [28]: s.print('--add', expr='l_int_a + l_int_b')
l_int_a + l_int_b : 855
# Step over a line of source code
Vitis [29]: s.nxt()
Info: ARM Cortex-A9 MPCore #0 (target 2) Running
Info: ARM Cortex-A9 MPCore #0 (target 2) Stopped at 0x100584 (Step)
main() at ../src/helloworld.c: 61
61: test_function(l_int_a, l_int_b);
# View stack trace
Vitis [30]: s.bt()
0 0x100584 main()+32:../src/helloworld.c, line 61
1 0x1007bc _start()+88:xil-crt0.S, line 119
2 unknown-pc
# Set a breakpoint at exit and resume execution
Vitis [31]: s.bpadd(addr='&exit')
Out[29]: <xsdb._breakpoint.Breakpoint at 0x7f016fd2c5e0>
Info: Breakpoint 1 status:
target 2: {Address: 0x1012ac Type: Hardware}
Info: Breakpoint 1 status:
target 3: {At col 5: Undefined identifier exit. Invalid expression}
Vitis [32]: s.con()
Info: ARM Cortex-A9 MPCore #0 (target 2) Running
Info: ARM Cortex-A9 MPCore #0 (target 2) Stopped at 0x1012ac (Breakpoint)
# View stack trace
Vitis [33]: s.bt()
0 0x1012ac exit()+0
1 0x71034f12Select_target_based_on_target_properties:
Vitis [2]: import xsdb
Vitis [3]: s = xsdb.start_debug_session()
# connecting to the target
Vitis [4]: s.connect(url="TCP:xhdbfarmrke9:3121")
tcfchan#0
Out[4]: 'tcfchan#0'
# check the jtag targets connected, the IDs listed with jtag targets are called node IDs
Vitis [5]: s.jtag_targets()
1 Digilent JTAG-SMT1 210203344713A ( is_pdi_programmable)
2 arm_dap (idcode 4ba00477 irlen 4 is_pdi_programmable)
3 xc7z020 (idcode 23727093 irlen 6 fpga is_pdi_programmable)
# check the targets connected, the IDs listed with targets are called target IDs
Vitis [6]: s.targets()
1 APU
2 ARM Cortex-A9 MPCore #0 (Breakpoint)
3 ARM Cortex-A9 MPCore #1 (Running)
4 xc7z020
# check jtag target properties of 2nd device (2nd ARM DAP). Note the target_ctx here.
Vitis [7]: s.jtag_targets('-t', filter="node_id == 2")
Out[7]:
{'jsn-JTAG-SMT1-210203344713A-4ba00477-0': {'target_ctx': 'jsn-JTAG-SMT1-210203344713A-4ba00477-0',
'level': 1,
'node_id': 2,
'is_open': 1,
'is_active': 1,
'is_current': 0,
'name': 'arm_dap',
'jtag_cable_name': 'Digilent JTAG-SMT1 210203344713A',
'state': '',
'jtag_cable_manufacturer': 'Digilent',
'jtag_cable_product': 'JTAG-SMT1',
'jtag_cable_serial': '210203344713A',
'idcode': '4ba00477',
'irlen': '4',
'is_fpga': 0,
'is_pdi_programmable': 0}}
# using the target context, select the targets associated with the JTAG target (2nd ARM DAP - node id = 2)
Vitis [8]: s.targets(filter="jtag_device_ctx == jsn-JTAG-SMT1-210203344713A-4ba0
...: 0477-0")
1 APU
2 ARM Cortex-A9 MPCore #0 (Breakpoint)
3 ARM Cortex-A9 MPCore #1 (Running)Debugging_prog_already_running_on_target:
Vitis [1]: import xsdb
Vitis [2]: s = xsdb.start_debug_session()
# connecting to the target
Vitis [3]: s.connect(url="TCP:xhdbfarmrke9:3121")
tcfchan#0
Out[3]: 'tcfchan#0'
# Select the target on which the program is running and specify the symbol file using the
# memmap command
Vitis [4]: s.target(2)
Out[4]: <xsdb._target.Target at 0x7f3167dd12e0>
Vitis [5]: s.memmap(file='test_jtag_uart.elf')
# When the symbol file is specified, the debugger maps the code on the target to the symbol
# file. bt command can be used to see the back trace. Further debug is possible, as shown in
# the first example
Vitis [6]: s.stop()
Info: ARM Cortex-A9 MPCore #0 (target 2) Stopped at 0x10101c (Suspended)
sleep_A9() at sleep.c: 63
63: } while (tCur < tEnd);
Vitis [7]: s.backtrace()
0 0x10101c sleep_A9()+56:sleep.c, line 63
1 0x100608 test_function()+76:../src/helloworld.c, line 78
2 0x100590 main()+44:../src/helloworld.c, line 61
3 0x1007ac _start()+88:xil-crt0.S, line 119
4 unknown-pcDebug_app_on_zu_plus_mpsoc:
Vitis [1]: import xsdb
Vitis [2]: s = xsdb.start_debug_session()
# connect to remote hw_server by specifying its url.
# If the hardware is connected to a local machine,-url option and the <url>
# are not needed. connect command returns the channel ID of the connection
Vitis [3]: s.connect(url="TCP:xhdbfarmrkk5:3121")
tcfchan#0
Out[3]: 'tcfchan#0'
# List available targets and select a target through its id.
# The targets are assigned IDs as they are discovered on the Jtag chain,
# so the IDs can change from session to session.
Vitis [4]: s.targets()
1 PS TAP
2 PMU
3 PL
4 PSU
5 RPU (Reset)
6 Cortex-R5 #0 (RPU Reset)
7 Cortex-R5 #1 (RPU Reset)
8 APU (L2 Cache Reset)
9 Cortex-A53 #0 (APU Reset)
10 Cortex-A53 #1 (APU Reset)
11 Cortex-A53 #2 (APU Reset)
12 Cortex-A53 #3 (APU Reset)
Vitis [5]: s.targets("--set", filter="name =~ PSU")
Out[5]: <xsdb._target.Target at 0x7fe9ca93bac0>
Vitis [6]: s.ta()
1 PS TAP
2 PMU
3 PL
4* PSU
5 RPU (Reset)
6 Cortex-R5 #0 (RPU Reset)
7 Cortex-R5 #1 (RPU Reset)
8 APU (L2 Cache Reset)
9 Cortex-A53 #0 (APU Reset)
10 Cortex-A53 #1 (APU Reset)
11 Cortex-A53 #2 (APU Reset)
12 Cortex-A53 #3 (APU Reset)
Vitis [7]: s.rst(type='system')
# Configure the FPGA. When the active target is not a FPGA device,
# the first FPGA device is configured
Vitis [8]: s.fpga(file='zcu102.bit')
100% 3.86MB 1.66MB/s 00:02ETA
Vitis [9]: s.targets(10)
Out[9]: <xsdb._target.Target at 0x7fe9a99347f0>
Vitis [10]: s.rst(type='cores')
Info: Cortex-A53 #0 (target 9) Stopped at 0xffff0000 (Reset Catch)
Info: Cortex-A53 #1 (target 10) Stopped at 0xffff0000 (Reset Catch)
Info: Cortex-A53 #2 (target 11) Stopped at 0xffff0000 (Reset Catch)
Info: Cortex-A53 #3 (target 12) Stopped at 0xffff0000 (Reset Catch)
# run fsbl to initialize PS
Vitis [11]: s.dow('fsbl_a53.elf')
Downloading Program -- fsbl_a53.elf
section, .text: 0xfffc0000 - 0xfffd65b7
section, .note.gnu.build-id: 0xfffd65b8 - 0xfffd65db
section, .init: 0xfffd6600 - 0xfffd6633
section, .fini: 0xfffd6640 - 0xfffd6673
section, .rodata: 0xfffd6680 - 0xfffd6b94
section, .sys_cfg_data: 0xfffd6bc0 - 0xfffd732b
section, .mmu_tbl0: 0xfffd8000 - 0xfffd800f
section, .mmu_tbl1: 0xfffd9000 - 0xfffdafff
section, .mmu_tbl2: 0xfffdb000 - 0xfffdefff
section, .data: 0xfffdf000 - 0xfffe02c7
section, .sbss: 0xfffe02c8 - 0xfffe02ff
section, .bss: 0xfffe0300 - 0xfffe297f
section, .heap: 0xfffe2980 - 0xfffe2d7f
section, .stack: 0xfffe2d80 - 0xfffe4d7f
section, .dup_data: 0xfffe4d80 - 0xfffe6047
section, .handoff_params: 0xfffe9e00 - 0xfffe9e87
section, .bitstream_buffer: 0xffff0040 - 0xfffffc3f
Successfully downloaded fsbl_a53.elf
Setting PC to Program Start Address 0xfffc0000
Vitis [12]: s.con()
Info: Cortex-A53 #1 (target 10) Running
Vitis [13]: s.stop()
Info: Cortex-A53 #1 (target 10) Stopped at 0xfffd2c7c (External Debug Request)
# run the application
Vitis [14]: s.dow('zcu102_hello.elf')
Downloading Program -- zcu102_hello.elf
section, .text: 0x00000000 - 0x000020b3
section, .init: 0x000020c0 - 0x000020f3
section, .fini: 0x00002100 - 0x00002133
section, .rodata: 0x00002140 - 0x00002360
section, .rodata1: 0x00002361 - 0x0000237f
section, .sdata2: 0x00002380 - 0x0000237f
section, .sbss2: 0x00002380 - 0x0000237f
section, .data: 0x00002380 - 0x00002bb7
section, .data1: 0x00002bb8 - 0x00002bbf
section, .note.gnu.build-id: 0x00002bc0 - 0x00002be3
section, .ctors: 0x00002be4 - 0x00002bff
section, .dtors: 0x00002c00 - 0x00002bff
section, .eh_frame: 0x00002c00 - 0x00002c03
section, .mmu_tbl0: 0x00003000 - 0x0000300f
section, .mmu_tbl1: 0x00004000 - 0x00005fff
section, .mmu_tbl2: 0x00006000 - 0x00009fff
section, .preinit_array: 0x0000a000 - 0x00009fff
section, .init_array: 0x0000a000 - 0x0000a007
section, .fini_array: 0x0000a008 - 0x0000a047
section, .sdata: 0x0000a048 - 0x0000a07f
section, .sbss: 0x0000a080 - 0x0000a07f
section, .tdata: 0x0000a080 - 0x0000a07f
section, .tbss: 0x0000a080 - 0x0000a07f
section, .bss: 0x0000a080 - 0x0000a0bf
section, .heap: 0x0000a0c0 - 0x0000c0bf
section, .stack: 0x0000c0c0 - 0x0000f0bf
Successfully downloaded zcu102_hello.elf
Setting PC to Program Start Address 0x00000000
Vitis [15]: s.bpadd(addr='main')
Out[15]: <xsdb._breakpoint.Breakpoint at 0x7fe9cae59cd0>
Info: Breakpoint 0 status:
target 6: {At col 4: Undefined identifier main. Invalid expression}
Info: Breakpoint 0 status:
target 7: {At col 4: Undefined identifier main. Invalid expression}
Info: Breakpoint 0 status:
target 9: {At col 4: Undefined identifier main. Invalid expression}
Info: Breakpoint 0 status:
target 10: {Address: 0xd00 Type: Hardware}
Info: Breakpoint 0 status:
target 11: {At col 4: Undefined identifier main. Invalid expression}
Info: Breakpoint 0 status:
target 12: {At col 4: Undefined identifier main. Invalid expression}
Vitis [16]: s.con()
Info: Cortex-A53 #1 (target 10) Running
Info: Cortex-A53 #1 (target 10) Stopped at 0xd08 (Breakpoint)
main() at ../src/helloworld.c: 29
29: int l_int_b = 20;
Vitis [17]: s.rrd()
r0: 00000000 r1: 00000000 r2: 00000000 r3: 00000004
r4: 0000000f r5: ffffffff r6: 0000001c r7: 00000002
r8: ffffffff r9: 00000000 r10: fd5c0090 r11: 00000000
r12: 00000000 r13: 00000000 r14: 00000000 r15: 00000000
r16: 00000000 r17: 00000000 r18: 00000000 r19: 00000000
r20: 00000000 r21: 00000000 r22: 00000000 r23: 00000000
r24: 00000000 r25: 00000000 r26: 00000000 r27: 00000000
r28: 00000000 r29: 0000e0a0 r30: 00000f34 sp: 0000e0a0
pc: 00000d08 cpsr: 600002cd vfp sys
dbg acpu_gic
Vitis [18]: s.stp()
Info: Cortex-A53 #1 (target 10) Running
Info: Cortex-A53 #1 (target 10) Stopped at 0xd10 (Step)
main() at ../src/helloworld.c: 30
30: int l_int_a = 40;
Vitis [19]: s.stp()
Info: Cortex-A53 #1 (target 10) Running
Info: Cortex-A53 #1 (target 10) Stopped at 0xd18 (Step)
main() at ../src/helloworld.c: 32
32: init_platform();
# Local variable value can be modified
Vitis [20]: s.locals()
l_int_b : 20
l_int_a : 40
Vitis [21]: s.locals(name='l_int_b', val=815)
Vitis [22]: s.locals(name='l_int_b')
l_int_b : 815
# Global variables and be displayed, and its value can be modified
Vitis [23]: s.print(expr='g_int_a')
g_int_a : 60
Vitis [24]: s.print(expr='g_int_a', val=9919)
Vitis [25]: s.print(expr='g_int_a')
g_int_a : 9919
# Expressions can be evaluated and its value can be displayed
Vitis [26]: s.print('--add', expr='l_int_a + l_int_b')
l_int_a + l_int_b : 855
# Step over a line of source code
Vitis [27]: s.nxt()
Info: Cortex-A53 #1 (target 10) Running
Info: Cortex-A53 #1 (target 10) Stopped at 0xd1c (Step)
main() at ../src/helloworld.c: 33
33: test_function(l_int_a, l_int_b);
# View stack trace
Vitis [28]: s.bt()
0 0xd1c main()+28:../src/helloworld.c, line 33
1 0xf34 _startup()+124:xil-crt0.S, line 157
# Set a breakpoint at exit and resume execution
Vitis [29]: s.bpadd(addr='&exit')
Info: Breakpoint 1 status:
target 6: {At col 5: Undefined identifier exit. Invalid expression}
Info: Breakpoint 1 status:
target 7: {At col 5: Undefined identifier exit. Invalid expression}
Info: Breakpoint 1 status:
target 9: {At col 5: Undefined identifier exit. Invalid expression}
Info: Breakpoint 1 status:
target 10: {Address: 0x1a90 Type: Hardware}
Info: Breakpoint 1 status:
target 11: {At col 5: Undefined identifier exit. Invalid expression}
Info: Breakpoint 1 status:
target 12: {At col 5: Undefined identifier exit. Invalid expression}
Out[29]: <xsdb._breakpoint.Breakpoint at 0x7fe9a35e9ca0>
Vitis [30]: s.con()
Info: Cortex-A53 #1 (target 10) Running
Vitis [31]: s.stop()
Info: Cortex-A53 #1 (target 10) Stopped at 0x192c (External Debug Request)
sleep_A53() at sleep.c: 71
71: } while (tCur < tEnd);
# View stack trace
Vitis [32]: s.bt()
0 0x192c sleep_A53()+44:sleep.c, line 71
1 0x192c sleep_A53()+44:sleep.c, line 70