When targets like APU/RPU/PSU/Versal are selected as active targets, physical memory is accessed during memory read/write commands. These targets use AXI-AP in Arm® DAP to access memory. The AXI-AP does not have access to the MMU or caches inside processor targets. However, the debugger flushes/invalidates the caches for every memory access command. Therefore, it is the same data on any target, APU/processor, even though the cache is enabled. Following are the examples.
Case 1: Write 0xAAAAAAAA to the location 0x30000000 from the processor target and read it from the APU target or processor target. The data is the same.
Case 2: Write 0x55AA55AA to the location 0x30000000 from the APU target and read it from the APU target or processor target. The data is the same in both targets. In the below screenshot, select target 1 on Zynq, which is APU, and write 0x55AA55AA. From Vitis, check the ddr_val variable from the processor target, which is updated as soon as we write from target1.