reg_dpu_isr - 4.1 English

DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)

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4.1 English

The reg_dpu_isr register represents the interrupt status of all cores in the DPUCZDX8G IP. The lower four bits of this register shows the interrupt status of up to four DPUCZDX8G cores. The details of reg_dpu_irq are shown in the following table.

Table 1. reg_dpu_isr
Register Address Offset Width Type Description
reg_dpu_isr 0x608 32 R [n] – DPUCZDX8G core n interrupt status