reg_dpu_base_addr - 4.1 English

DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)
Document ID
PG338
Release Date
2023-01-23
Version
4.1 English

The reg_dpu_base_addr register is used to indicate the address of input image and parameters for each DPUCZDX8G in external memory. The width of a DPUCZDX8G base address is 40 bits so it can support an address space up to 1 TB. All registers are 32 bits wide, so two registers are required to represent a 40-bit wide base address. reg_dpu0_base_addr0_l represents the lower 32 bits of base_address0 in DPUCZDX8G core0 and reg_dpu0_base_addr0_h represents the upper eight bits of base_address0 in DPUCZDX8G core0.

There are eight groups of DPUCZDX8G base addresses for each DPUCZDX8G core and thus 32 groups of DPUCZDX8G base addresses for up to four DPUCZDX8G cores. The details of reg_dpu_base_addr are shown in the following table.

Table 1. reg_dpu_base_addr
Register Address Offset Width Type Description
reg_dpu0_base_addr0_l 0x224 32 R/W The lower 32 bits of base_address0 of DPUCZDX8G core0.
reg_dpu0_base_addr0_h 0x228 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address0 of DPUCZDX8G core0.
reg_dpu0_base_addr1_l 0x22C 32 R/W The lower 32 bits of base_address1 of DPUCZDX8G core0.
reg_dpu0_base_addr1_h 0x230 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address1 of DPUCZDX8G core0.
reg_dpu0_base_addr2_l 0x234 32 R/W The lower 32 bits of base_address2 of DPUCZDX8G core0.
reg_dpu0_base_addr2_h 0x238 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address2 of DPUCZDX8G core0.
reg_dpu0_base_addr3_l 0x23C 32 R/W The lower 32 bits of base_address3 of DPUCZDX8G core0.
reg_dpu0_base_addr3_h 0x240 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address3 of DPUCZDX8G core0.
reg_dpu0_base_addr4_l 0x244 32 R/W The lower 32 bits of base_address4 of DPUCZDX8G core0.
reg_dpu0_base_addr4_h 0x248 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address4 of DPUCZDX8G core0.
reg_dpu0_base_addr5_l 0x24C 32 R/W The lower 32 bits of base_address5 of DPUCZDX8G core0.
reg_dpu0_base_addr5_h 0x250 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address5 of DPUCZDX8G core0.
reg_dpu0_base_addr6_l 0x254 32 R/W The lower 32 bits of base_address6 of DPUCZDX8G core0.
reg_dpu0_base_addr6_h 0x258 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address6 of DPUCZDX8G core0.
reg_dpu0_base_addr7_l 0x25C 32 R/W The lower 32 bits of base_address7 of DPUCZDX8G core0.
reg_dpu0_base_addr7_h 0x260 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address7 of DPUCZDX8G core0.
reg_dpu1_base_addr0_l 0x324 32 R/W The lower 32 bits of base_address0 of DPUCZDX8G core1.
reg_dpu1_base_addr0_h 0x328 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address0 of DPUCZDX8G core1.
reg_dpu1_base_addr1_l 0x32C 32 R/W The lower 32 bits of base_address1 of DPUCZDX8G core1.
reg_dpu1_base_addr1_h 0x330 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address1 of DPUCZDX8G core1.
reg_dpu1_base_addr2_l 0x334 32 R/W The lower 32 bits of base_address2 of DPUCZDX8G core1.
reg_dpu1_base_addr2_h 0x338 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address2 of DPUCZDX8G core1.
reg_dpu1_base_addr3_l 0x33C 32 R/W The lower 32 bits of base_address3 of DPUCZDX8G core1.
reg_dpu1_base_addr3_h 0x340 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address3 of DPUCZDX8G core1.
reg_dpu1_base_addr4_l 0x344 32 R/W The lower 32 bits of base_address4 of DPUCZDX8G core1.
reg_dpu1_base_addr4_h 0x348 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address4 of DPUCZDX8G core1.
reg_dpu1_base_addr5_l 0x34C 32 R/W The lower 32 bits of base_address5 of DPUCZDX8G core1.
reg_dpu1_base_addr5_h 0x350 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address5 of DPUCZDX8G core1.
reg_dpu1_base_addr6_l 0x354 32 R/W The lower 32 bits of base_address6 of DPUCZDX8G core1.
reg_dpu1_base_addr6_h 0x358 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address6 of DPUCZDX8G core1.
reg_dpu1_base_addr7_l 0x35C 32 R/W The lower 32 bits of base_address7 of DPUCZDX8G core1.
reg_dpu1_base_addr7_h 0x360 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address7 of DPUCZDX8G core1.
reg_dpu2_base_addr1_l 0x42C 32 R/W The lower 32 bits of base_address1 of DPUCZDX8G core2.
reg_dpu2_base_addr1_h 0x430 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address1 of DPUCZDX8G core2.
reg_dpu2_base_addr2_l 0x434 32 R/W The lower 32 bits of base_address2 of DPUCZDX8G core2.
reg_dpu2_base_addr2_h 0x438 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address2 of DPUCZDX8G core2.
reg_dpu2_base_addr3_l 0x43C 32 R/W The lower 32 bits of base_address3 of DPUCZDX8G core2.
reg_dpu2_base_addr3_h 0x440 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address3 of DPUCZDX8G core2.
reg_dpu2_base_addr4_l 0x444 32 R/W The lower 32 bits of base_address4 of DPUCZDX8G core2.
reg_dpu2_base_addr4_h 0x448 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address4 of DPUCZDX8G core2.
reg_dpu2_base_addr5_l 0x44C 32 R/W The lower 32 bits of base_address5 of DPUCZDX8G core2.
reg_dpu2_base_addr5_h 0x450 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address5 of DPUCZDX8G core2.
reg_dpu2_base_addr6_l 0x454 32 R/W The lower 32 bits of base_address6 of DPUCZDX8G core2.
reg_dpu2_base_addr6_h 0x458 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address6 of DPUCZDX8G core2.
reg_dpu2_base_addr7_l 0x45C 32 R/W The lower 32 bits of base_address7 of DPUCZDX8G core2.
reg_dpu2_base_addr7_h 0x460 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address7 of DPUCZDX8G core2.
reg_dpu3_base_addr0_l 0x524 32 R/W The lower 32 bits of base_address0 of DPUCZDX8G core3.
reg_dpu3_base_addr0_h 0x528 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address0 of DPUCZDX8G core3.
reg_dpu3_base_addr1_l 0x52C 32 R/W The lower 32 bits of base_address1 of DPUCZDX8G core3.
reg_dpu3_base_addr1_h 0x530 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address1 of DPUCZDX8G core3.
reg_dpu3_base_addr2_l 0x534 32 R/W The lower 32 bits of base_address2 of DPUCZDX8G core3.
reg_dpu3_base_addr2_h 0x538 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address2 of DPUCZDX8G core3.
reg_dpu3_base_addr3_l 0x53C 32 R/W The lower 32 bits of base_address3 of DPUCZDX8G core3.
reg_dpu3_base_addr3_h 0x540 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address3 of DPUCZDX8G core3.
reg_dpu3_base_addr4_l 0x544 32 R/W The lower 32 bits of base_address4 of DPUCZDX8G core3.
reg_dpu3_base_addr4_h 0x548 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address4 of DPUCZDX8G core3.
reg_dpu3_base_addr5_l 0x54C 32 R/W The lower 32 bits of base_address5 of DPUCZDX8G core3.
reg_dpu3_base_addr5_h 0x550 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address5 of DPUCZDX8G core3.
reg_dpu3_base_addr6_l 0x554 32 R/W The lower 32 bits of base_address6 of DPUCZDX8G core3
reg_dpu3_base_addr6_h 0x558 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address6 of DPUCZDX8G core3.
reg_dpu3_base_addr7_l 0x55C 32 R/W The lower 32 bits of base_address7 of DPUCZDX8G core3.
reg_dpu3_base_addr7_h 0x560 32 R/W The lower 8 bits in the register represent the upper 8 bits of base_address7 of DPUCZDX8G core3.