Resource Utilization - 4.1 English

DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)
Document ID
PG338
Release Date
2023-01-23
Version
4.1 English

The resource utilization of a sample DPUCZDX8G single core project is as follows. The data is based on the ZCU102 platform with low RAM usage, channel augmentation, alu parallel = PP/2, conv: leaky ReLU + ReLU6, alu: ReLU6 features, high DSP usage, and Argmax enabled.

Table 1. Resources of Different DPUCZDX8G Architectures
DPUCZDX8G Architecture LUT Register Block RAM DSP
B512 26922 34543 72 118
B800 29721 41147 90 166
B1024 34074 48057 104 230
B1152 32169 47374 121 222
B1600 38418 58831 126 326
B2304 42127 68829 165 438
B3136 46714 79710 208 566
B4096 52161 98249 255 710

Another example of a DPUCZDX8G single core project is based on the ZCU104 platform. In this project, the image and weights buffer utilize UltraRAM. The project is configured with low RAM usage, channel augmentation, alu parallel = PP/2, conv: leaky ReLU + ReLU6, alu: ReLU6 features, and high DSP usage. The resource utilization of this project is as follows.

Table 2. Resources of DPUCZDX8G using UltraRAM
DPUCZDX8G Architecture LUT Register Block RAM UltraRAM DSP
B512 26767 34538 0 18 118
B800 29578 41153 0 40 166
B1024 33752 48093 0 26 230
B1152 31901 47797 0 44 222
B1600 38197 58859 0 56 326
B2304 41736 69604 0 60 438
B3136 46260 80079 0 64 566
B4096 51843 98567 0 68 710