Number of DPU Cores - 4.1 English

DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)

Document ID
Release Date
4.1 English

A maximum of four cores can be selected in one DPUCZDX8G IP. Multiple DPUCZDX8G cores can be used to achieve higher performance, at the expense of programmable logic resources.

Contact your local Xilinx sales representative if you require more than four cores.