Reset - 4.1 English

DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)

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4.1 English

There are three input clocks for the DPUCZDX8G IP and each clock has a corresponding reset. Each reset must be synchronous to its corresponding clock. If the related clocks and resets are not synchronized, correct operation of the DPU cannot be guaranteed. A Processor System Reset IP block is recommended to generate a synchronized reset signal. The reference design is shown here.

Figure 1. DPU Reset Circuit Example