Channel Augmentation - 4.1 English

DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)

Document ID
PG338
Release Date
2023-01-23
Version
4.1 English

Channel augmentation is an optional feature for improving the efficiency of the DPUCZDX8G when the number of input channels is much lower than the available channel parallelism. For example, the input channel of the first layer in most CNNs is three, which does not fully use all the available hardware channels. If the number of input channels is larger than the channel parallelism, channel augmentation can still be utilized.

Thus, channel augmentation can improve the total efficiency for most CNNs, but it will cost extra logic resources. The following table illustrates the extra LUT resources used with channel augmentation and the statistics are for reference.

Table 1. Extra LUTs of DPUCZDX8G with Channel Augmentation
DPUCZDX8G Architecture Extra LUTs with Channel Augmentation
B512 3121
B800 2624
B1024 3133
B1152 1744
B1600 2476
B2304 1710
B3136 1946
B4096 1701