Register Clock - 4.1 English

DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)

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4.1 English

s_axi_aclk is used for the register configuration module. This module receives the DPUCZDX8G configuration though the S_AXI interface. The S_AXI clock can be common with the M-AXI clock or an independent clock. The DPUCZDX8G configuration registers are updated at a very low frequency and most of those registers are set only at the start of a task. Because the M-AXI domain directly impacts DPU performance, Xilinx recommends that the user configure the S-AXI is an independent clock with a frequency of 100MHz, while targeting a higher frequency for the M-AXI clocks. 

In the Vitis flow, the platform may provide only two clocks for the DPUCZDX8G IP. In this case, the S_AXI clock must be configured as common with the M-AXI clock  and target the higher frequency.