IP Facts - 4.1 English

DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)

Document ID
Release Date
4.1 English
DPUCZDX8G IP Facts Table
Core Specifics
Supported Device Family Zynq® UltraScale+™ MPSoC Family
Supported User Interfaces Memory-mapped AXI interfaces
Resources See DPU Configuration.
Provided with Core
Design Files Encrypted RTL
Example Design Verilog
Constraints File Xilinx Design Constraints (XDC)
Supported S/W Driver Included in PetaLinux
Test Bench Not Provided
Simulation Model Not Provided
Tested Design Flows
Design Entry Vivado® Design Suite and Vitis™ unified software platform
Simulation N/A
Synthesis Vivado® Synthesis
Xilinx Support web page
  1. Linux OS and driver support information are available from DPUCZDX8G TRD or Vitis™ AI development kit.
  2. For the supported tool versions, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).
  3. The DPUCZDX8G is driven by instructions generated by the Vitis AI compiler. When the target neural network (NN), DPUCZDX8G hardware architecture, or AXI data width is changed, the related .xmodel file which contains DPUCZDX8G instructions must be regenerated with the updated arch.json file.
  4. The DPU does not support hw_emu function. The reasons are as follows:
    • The RTL code of DPU is encrypted. Vitis™ does not analyze the source code.
    • The DPU is a co-processor and would require a highly complex test environment for adequate design verification.