Clocking - 4.1 English

DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)

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4.1 English

There are three clock domains in the DPUCZDX8G IP, associated with register configuration, the DPU data plane and computation. The three input clocks can be configured independently in order to match system and performance requirements. Therefore, the corresponding reset for the three input clocks must be configured correctly.