Some models found in the Xilinx Model Zoo may not be supported on smaller DPU architectures due to feature map size limitations. The following list specifies the models that are not supported on these smaller DPU architectures. The B4096 supports all models listed in the ZCU102 model-performance listings on GitHub: https://github.com/Xilinx/Vitis-AI/tree/master/model_zoo#model-performance.
DPUCZDX8G Architecture | Unsupported models |
---|---|
B512 | inception_resnet_v2_tf |
vgg_16_tf | |
vgg_19_tf | |
facerec_resnet20 | |
facerec_resnet64 | |
facerec-resnet20_mixed_pt | |
efficientnet-b0_tf2 | |
efficientdet_d2_tf | |
ocr_pt | |
textmountain_pt | |
SA_gate_base_pt | |
HRNet_pt | |
B800 | vgg_16_tf |
vgg_19_tf | |
facerec_resnet20 | |
facerec_resnet64 | |
facerec-resnet20_mixed_pt | |
efficientnet-b0_tf2 | |
efficientdet_d2_tf | |
ocr_pt | |
textmountain_pt | |
SA_gate_base_pt | |
B1024 | inception_resnet_v2_tf |
vgg_16_tf | |
vgg_19_tf | |
facerec_resnet20 | |
facerec_resnet64 | |
facerec-resnet20_mixed_pt | |
efficientdet_d2_tf | |
ocr_pt | |
textmountain_pt | |
SA_gate_base_pt | |
B1152 | vgg_16_tf |
vgg_19_tf | |
efficientnet-b0_tf2 | |
ocr_pt | |
SA_gate_base_pt | |
B1600 | vgg_16_tf |
vgg_19_tf | |
facerec_resnet20 | |
facerec_resnet64 | |
facerec-resnet20_mixed_pt | |
textmountain_pt | |
SA_gate_base_pt | |
B2304 | vgg_16_tf |
vgg_19_tf | |
SA_gate_base_pt | |
B3136 | vgg_16_tf |
vgg_19_tf | |
SA_gate_base_pt |