Verification, Compliance, and Interoperability - 1.1 English

Video Scene Change Detection LogiCORE IP Product Guide (PG322)

Document ID
Release Date
1.1 English


A highly parameterizable test bench was used to test the Video scene change detection in Vitis High-Level Synthesis (HLS). Testing included the following:

  • Register accesses
  • Processing multiple frames of data
  • Varying IP throughput and pixel data width
  • Testing the Video Scene Change Detection IP with memory mapped AXI4 interface or AXI4-Stream interface
  • Testing of various frame sizes
  • Varying parameter settings
  • Testing Video Scene Change Detection for multiple input streams in memory base mode

Hardware Testing

The Video Scene Change Detection core has been validated at AMD to represent many different parameterizations. A test design was developed for the core that incorporated a Zynq UltraScale+ MPSoC processor, AXI4-Lite interconnect, and various other peripherals. The MPSoC processor is responsible for:

  • Programing the video scene change detection IP registers
  • Launching the test
  • Reporting the Pass/Fail status of the test and any errors that were found


The core slave (input) and master (output) AXI4-Stream interface can work directly with any core that produces RGB, YUV 4:4:4, YUV 4:2:2, or YUV 4:2:0 video data.