There is a memory mapped AXI4 interface
named m_axi_mm_video. The memory mapped AXI4 interface runs on the ap_clk clock domain. The signals follow the specification as defined in the
Vivado Design Suite: AXI Reference
Guide (UG1037). The following table shows the pixel
formats in the memory supported by the Video Scene Change Detection
IP.
Table 1. Memory Mode Pixel Formats
| Video Format |
Description |
Bits Per Component |
Bytes Per Pixel |
| Y8 |
Packed luma only |
8 |
1 byte per pixel |
| Y10 |
Packed luma only |
10 |
4 bytes per 3 pixel |
The following sections explain the expected pixel mappings in memory for
each of the listed formats.
Y8 Format
Packed luma-only eight bits per component. Every luma-only pixel in the
memory is represented with 8 bits. The images need to be stored in the memory in raster
order, that is, top-left pixel first, bottom-right pixel last. Y8 is presented as YUV 4:4:4
on the
AXI4-Stream interface.
Y10 Format
Packed luma-only 10 bits per component. Every three luma-only pixels in the
memory is represented with 32 bits. The images need be stored in the memory in raster order,
that is, top-left pixel first, bottom-right pixel last. Y10 is presented as YUV 4:4:4 on the
AXI4-Stream interface.
Table 3. Y10 Format
| 9:0 |
19:10 |
29:20 |
31:30 |
| Y0 |
Y1 |
Y2 |
X |