The AXI4-Lite interface allows you to
dynamically control the parameters within the core. The configuration can be accomplished by
using an AXI4-Lite master state machine, an embedded
Arm®
processor, or a soft system processor such as
MicroBlaze™
processor. The Video Scene Change Detection IP can be controlled through the AXI4-Lite interface by using functions provided by the driver in the AMD Vitis™
software platform. Another method is by performing read and write
transactions to the register space, but this method is only used when the first method is
not available. The following table shows the AXI4-Lite
control interface signals. This interface runs at the ap_clk clock.
| Signal Name | I/O | Width | Description |
|---|---|---|---|
| s_axi_ctrl_aresetn | I | 1 | Reset |
| s_axi_ctrl_aclk | I | 1 | Clock |
| s_axi_ctrl_awaddr | I | 18 | Write Address |
| s_axi_ctrl_awprot | I | 3 | Write Address Protection |
| s_axi_ctrl_awvalid | I | 1 | Write Address Valid |
| s_axi_ctrl_awready | O | 1 | Write Address Ready |
| s_axi_ctrl_wdata | I | 32 | Write Data |
| s_axi_ctrl_wstrb | I | 4 | Write Data Strobe |
| s_axi_ctrl_wvalid | I | 1 | Write Data Valid |
| s_axi_ctrl_wready | O | 1 | Write Data Ready |
| s_axi_ctrl_bresp | O | 2 | Write Response |
| s_axi_ctrl_bvalid | O | 1 | Write Response Valid |
| s_axi_ctrl_bready | I | 1 | Write Response Ready |
| s_axi_ctrl_araddr | I | 18 | Read Address |
| s_axi_ctrl_arprot | I | 3 | Read Address Protection |
| s_axi_ctrl_arvalid | I | 1 | Read Address Valid |
| s_axi_ctrl_aready | O | 1 | Read Address Ready |
| s_axi_ctrl_rdata | O | 32 | Read Data |
| s_axi_ctrl_rresp | O | 2 | Read Data Response |
| s_axi_ctrl_rvalid | O | 1 | Read Data Valid |
| s_axi_ctrl_rready | I | 1 | Read Data Ready |