|
Core Specifics |
| Supported Device Family
1
|
AMD Versal™
adaptive SoC,
AMD UltraScale+™
Families, AMD UltraScale™
Architecture, AMD Zynq™ 7000 SoC, 7 series
|
| Supported User Interfaces |
AXI4-Master, AXI4-Lite, AXI4-Stream
2
|
| Resources |
Performance and Resource Use web
page
|
| Provided with Core
|
| Design Files |
Not Provided |
| Example Design |
Yes |
| Test Bench |
Not Provided |
| Constraints File |
Xilinx Design Constraints (XDC) |
| Simulation Model |
Encrypted RTL |
| Supported S/W Driver
3
|
Standalone, Linux V4L2 |
| Tested Design Flows
4
|
| Design Entry |
AMD Vivado™ Design Suite
|
| Simulation |
For supported simulators, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973). |
| Synthesis |
AMD Vivado™
Synthesis |
| Support |
| Release Notes and Known Issues |
Master Answer Record: 70293
|
| All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775
|
|
Support web
page
|
- For a complete list of supported devices, see
the Vivado IP catalog.
- Video protocol as defined in the "Video IP:
AXI Feature Adoption" section of
Vivado Design Suite: AXI Reference
Guide (UG1037).
- Standalone driver details can be found in the
Vitis directory
(<install_directory>/Vitis/<release>/data/embeddedsw/doc/xilinx_drivers.htm). Linux OS and driver
support information is available from the Wiki
page.
- For the supported versions of the tools, see
the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
- Resource utilization is available at Performance and Resource Use web
page.
|